Differential coder as dedicated block + deplacement to datalink layer for pre-convolutionnal coder differential encoding capability

README

@@ -1,7 +1,6 @@
 -------------------------------
 Project: EurySPACE
 Version: 1.0.0
-Date: 2016/13/03
 -------------------------------
 Author(s):
 Guillaume REMBERT

hw/rtl/ccsds_rxtx/ccsds_rxtx.core

@@ -21,6 +21,7 @@ files =
  ccsds_rx_physical_layer.vhd
  ccsds_tx.vhd
  ccsds_tx_coder.vhd
+ ccsds_tx_coder_differential.vhd
  ccsds_tx_datalink_layer.vhd
  ccsds_tx_filter.vhd
  ccsds_tx_footer.vhd

hw/rtl/ccsds_rxtx/ccsds_rxtx_bench.vhd

@@ -26,6 +26,7 @@
 ---- 2016/11/04: adding lfsr sub-component test ressources
 ---- 2016/11/05: adding mapper sub-component test ressources
 ---- 2016/11/08: adding srrc + filter sub-component test ressources
+---- 2016/11/18: adding differential coder sub-component
 -------------------------------
 --TODO: functions for sub-components interactions and checks (wb_read, wb_write, buffer_read, ...)
 
@@ -51,6 +52,9 @@ entity ccsds_rxtx_bench is
     -- BUFFER
     CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE : integer := 32;
     CCSDS_RXTX_BENCH_BUFFER0_SIZE : integer := 16;
+    -- CODER DIFFERENTIAL
+    CCSDS_RXTX_BENCH_CODER_DIFF0_BITS_PER_CODEWORD: integer := 4;
+    CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE: integer := 32;
     -- CRC
     CCSDS_RXTX_BENCH_CRC0_DATA: std_logic_vector := x"313233343536373839";
     CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED: boolean := false;
@@ -64,8 +68,7 @@ entity ccsds_rxtx_bench is
     CCSDS_RXTX_BENCH_CRC0_XOR: std_logic_vector := x"0000";
     -- FILTER
     CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE: integer := 32;
-    CCSDS_RXTX_BENCH_FILTER0_MAPPER_DIFFERENTIAL_CODER: boolean := false;
-    CCSDS_RXTX_BENCH_FILTER0_OFFSET_PSK: boolean := true;
+    CCSDS_RXTX_BENCH_FILTER0_OFFSET_IQ: boolean := true;
     CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO: integer := 4;
     CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF: real := 0.5;
     CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH: integer := 16;
@@ -86,7 +89,6 @@ entity ccsds_rxtx_bench is
 		-- MAPPER
 		CCSDS_RXTX_BENCH_MAPPER0_BITS_PER_SYMBOL: integer := 2;
 		CCSDS_RXTX_BENCH_MAPPER0_DATA_BUS_SIZE: integer := 32;
-    CCSDS_RXTX_BENCH_MAPPER0_DIFFERENTIAL_CODER: boolean := true;
     CCSDS_RXTX_BENCH_MAPPER0_MODULATION_TYPE: integer := 1;
     -- SERDES
     CCSDS_RXTX_BENCH_SERDES0_DEPTH: integer := 32;
@@ -97,6 +99,8 @@ entity ccsds_rxtx_bench is
     CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH: integer := 16;
     -- simulation/test parameters
     CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD: time := 10 ns;
+    CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD: time := 10 ns;
+    CCSDS_RXTX_BENCH_CODER_DIFF0_WORDS_NUMBER: integer := 1000;
     CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD: time := 10 ns;
     CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE: integer:= 8;
     CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER: integer:= 25;
@@ -106,6 +110,7 @@ entity ccsds_rxtx_bench is
     CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER: integer := 25;
     CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD: time := 10 ns;
     CCSDS_RXTX_BENCH_MAPPER0_CLK_PERIOD: time := 10 ns;
+    CCSDS_RXTX_BENCH_MAPPER0_WORDS_NUMBER: integer := 1000;
     CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD: time := 20 ns;
     CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER: integer := 5000;
     CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW: boolean := true;
@@ -114,6 +119,7 @@ entity ccsds_rxtx_bench is
     CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER: integer := 25;
     CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD: time := 10 ns;
     CCSDS_RXTX_BENCH_START_BUFFER_WAIT_DURATION: time := 2000 ns;
+    CCSDS_RXTX_BENCH_START_CODER_DIFF_WAIT_DURATION: time := 2000 ns;
     CCSDS_RXTX_BENCH_START_CRC_WAIT_DURATION: time := 2000 ns;
     CCSDS_RXTX_BENCH_START_FILTER_WAIT_DURATION: time := 2000 ns;
     CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION: time := 2000 ns;
@@ -151,6 +157,8 @@ architecture behaviour of ccsds_rxtx_bench is
       rx_irq_o: out std_logic;
       tx_clk_i: in std_logic;
       tx_dat_ser_i: in std_logic;
+      tx_buf_ful_o: out std_logic;
+      tx_idl_o: out std_logic;
       tx_sam_i_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
       tx_sam_q_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
       tx_clk_o: out std_logic;
@@ -174,17 +182,31 @@ architecture behaviour of ccsds_rxtx_bench is
       dat_val_o: out std_logic
     );
   end component;
+  component ccsds_tx_coder_differential is
+    generic(
+      CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
+      CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
+    );
+    port(
+      clk_i: in std_logic;
+      dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
+      dat_val_i: in std_logic;
+      rst_i: in std_logic;
+      dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
+      dat_val_o: out std_logic
+    );
+  end component;
   component ccsds_rxtx_crc is
-  generic(
-    constant CCSDS_RXTX_CRC_DATA_LENGTH: integer;
-    constant CCSDS_RXTX_CRC_FINAL_XOR: std_logic_vector;
-    constant CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED: boolean;
-    constant CCSDS_RXTX_CRC_INPUT_REFLECTED: boolean;
-    constant CCSDS_RXTX_CRC_LENGTH: integer;
-    constant CCSDS_RXTX_CRC_OUTPUT_REFLECTED: boolean;
-    constant CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector;
-    constant CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED: boolean;
-    constant CCSDS_RXTX_CRC_SEED: std_logic_vector
+    generic(
+      CCSDS_RXTX_CRC_DATA_LENGTH: integer;
+      CCSDS_RXTX_CRC_FINAL_XOR: std_logic_vector;
+      CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED: boolean;
+      CCSDS_RXTX_CRC_INPUT_REFLECTED: boolean;
+      CCSDS_RXTX_CRC_LENGTH: integer;
+      CCSDS_RXTX_CRC_OUTPUT_REFLECTED: boolean;
+      CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector;
+      CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED: boolean;
+      CCSDS_RXTX_CRC_SEED: std_logic_vector
   );
   port(
     clk_i: in std_logic;
@@ -201,7 +223,7 @@ architecture behaviour of ccsds_rxtx_bench is
   end component;
   component ccsds_tx_filter is
     generic(
-      CCSDS_TX_FILTER_OFFSET_PSK: boolean;
+      CCSDS_TX_FILTER_OFFSET_IQ: boolean;
       CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
       CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
       CCSDS_TX_FILTER_MODULATION_TYPE: integer;
@@ -255,7 +277,6 @@ architecture behaviour of ccsds_rxtx_bench is
   component ccsds_tx_mapper is
     generic(
       CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer;
-      CCSDS_TX_MAPPER_DIFFERENTIAL_CODER: boolean;
       CCSDS_TX_MAPPER_MODULATION_TYPE: integer;
       CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer
     );
@@ -312,6 +333,7 @@ architecture behaviour of ccsds_rxtx_bench is
   constant CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD: time := CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD;
 -- internal variables
   signal bench_ena_buffer0_random_data: std_logic := '0';
+  signal bench_ena_coder_diff0_random_data: std_logic := '0';
   signal bench_ena_crc0_random_data: std_logic := '0';
   signal bench_ena_filter0_random_data: std_logic := '0';
   signal bench_ena_framer0_random_data: std_logic := '0';
@@ -344,6 +366,11 @@ architecture behaviour of ccsds_rxtx_bench is
   signal bench_sti_buffer0_next_data: std_logic;
   signal bench_sti_buffer0_data: std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
   signal bench_sti_buffer0_data_valid: std_logic;
+  -- coder differential
+  signal bench_sti_coder_diff0_clk: std_logic;
+  signal bench_sti_coder_diff0_rst: std_logic;
+  signal bench_sti_coder_diff0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
+  signal bench_sti_coder_diff0_dat_val: std_logic;
   -- crc
   signal bench_sti_crc0_clk: std_logic;
   signal bench_sti_crc0_rst: std_logic;
@@ -402,6 +429,8 @@ architecture behaviour of ccsds_rxtx_bench is
   signal bench_res_rxtx0_rx_irq: std_logic;
   -- tx
   signal bench_res_rxtx0_tx_clk: std_logic;
+  signal bench_res_rxtx0_tx_buf_ful: std_logic;  
+  signal bench_res_rxtx0_tx_idl: std_logic;
   signal bench_res_rxtx0_tx_samples_i: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
   signal bench_res_rxtx0_tx_samples_q: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
   signal bench_res_rxtx0_tx_ena: std_logic;
@@ -410,6 +439,9 @@ architecture behaviour of ccsds_rxtx_bench is
   signal bench_res_buffer0_buffer_full: std_logic;
   signal bench_res_buffer0_data: std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
   signal bench_res_buffer0_data_valid: std_logic;
+  -- coder differential
+  signal bench_res_coder_diff0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
+  signal bench_res_coder_diff0_dat_val: std_logic;
   -- crc
   signal bench_res_crc0_busy: std_logic;
   signal bench_res_crc0_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
@@ -483,6 +515,8 @@ architecture behaviour of ccsds_rxtx_bench is
         tx_sam_i_o => bench_res_rxtx0_tx_samples_i,
         tx_sam_q_o => bench_res_rxtx0_tx_samples_q,
         tx_clk_o => bench_res_rxtx0_tx_clk,
+        tx_buf_ful_o => bench_res_rxtx0_tx_buf_ful,
+        tx_idl_o => bench_res_rxtx0_tx_idl,
         tx_ena_o => bench_res_rxtx0_tx_ena
       );
     -- Instance(s) of sub-components under test
@@ -502,6 +536,19 @@ architecture behaviour of ccsds_rxtx_bench is
         dat_nxt_i => bench_sti_buffer0_next_data,
         dat_o => bench_res_buffer0_data
       );
+    coder_differential_000: ccsds_tx_coder_differential
+      generic map(
+        CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_RXTX_BENCH_CODER_DIFF0_BITS_PER_CODEWORD,
+        CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE
+      )
+      port map(
+        clk_i => bench_sti_coder_diff0_clk,
+        rst_i => bench_sti_coder_diff0_rst,
+        dat_val_i => bench_sti_coder_diff0_dat_val,
+        dat_i => bench_sti_coder_diff0_dat,
+        dat_val_o => bench_res_coder_diff0_dat_val,
+        dat_o => bench_res_coder_diff0_dat
+      );
     crc_000: ccsds_rxtx_crc
       generic map(
         CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_DATA'length/8,
@@ -577,7 +624,7 @@ architecture behaviour of ccsds_rxtx_bench is
     filter000: ccsds_tx_filter
       generic map(
         CCSDS_TX_FILTER_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
-        CCSDS_TX_FILTER_OFFSET_PSK => CCSDS_RXTX_BENCH_FILTER0_OFFSET_PSK,
+        CCSDS_TX_FILTER_OFFSET_IQ => CCSDS_RXTX_BENCH_FILTER0_OFFSET_IQ,
         CCSDS_TX_FILTER_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH,
         CCSDS_TX_FILTER_MODULATION_TYPE => CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE,
         CCSDS_TX_FILTER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL
@@ -628,7 +675,6 @@ architecture behaviour of ccsds_rxtx_bench is
       generic map(
         CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_MAPPER0_DATA_BUS_SIZE,
         CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_RXTX_BENCH_MAPPER0_MODULATION_TYPE,
-        CCSDS_TX_MAPPER_DIFFERENTIAL_CODER => CCSDS_RXTX_BENCH_MAPPER0_DIFFERENTIAL_CODER,
         CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_MAPPER0_BITS_PER_SYMBOL
       )
       port map(
@@ -644,8 +690,7 @@ architecture behaviour of ccsds_rxtx_bench is
       generic map(
         CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE,
         CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE,
-        CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL,
-        CCSDS_TX_MAPPER_DIFFERENTIAL_CODER => CCSDS_RXTX_BENCH_FILTER0_MAPPER_DIFFERENTIAL_CODER
+        CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL
       )
       port map(
         clk_i => bench_sti_filter0_mapper_clk,
@@ -790,6 +835,20 @@ architecture behaviour of ccsds_rxtx_bench is
         wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
       end process;
     --=============================================================================
+    -- Begin of bench_sti_coder_diff0_clk
+    -- bench_sti_coder_diff0_clk generation
+    --=============================================================================
+    -- read: 
+    -- write: bench_sti_coder_diff0_clk
+    -- r/w: 
+    BENCH_STI_CODER_DIFF0_CLKP : process
+      begin
+        bench_sti_coder_diff0_clk <= '1';
+        wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD/2;
+        bench_sti_coder_diff0_clk <= '0';
+        wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD/2;
+      end process;
+    --=============================================================================
     -- Begin of bench_sti_crc0_clkp
     -- bench_sti_crc0_clk generation
     --=============================================================================
@@ -938,6 +997,25 @@ architecture behaviour of ccsds_rxtx_bench is
         wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
       end process;
     --=============================================================================
+    -- Begin of bench_sti_coder_diff0_datap
+    -- bench_sti_coder_diff0_random_data generation
+    --=============================================================================
+    -- read: bench_ena_coder_diff0_random_data
+    -- write: bench_sti_coder_diff0_dat
+    -- r/w: 
+    BENCH_STI_CODER_DIFF0_DATAP : process
+      variable seed1, seed2 : positive := CCSDS_RXTX_BENCH_SEED;
+      variable random : std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
+      begin
+        if (bench_ena_coder_diff0_random_data = '1') then
+          sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE,seed1,seed2,random);
+          sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE,seed1,seed2,random);
+          bench_sti_coder_diff0_dat <= random;
+        end if;
+        wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
+      end process;
+
+    --=============================================================================
     -- Begin of bench_sti_crc0_datap
     -- bench_sti_crc0_random_data generation
     --=============================================================================
@@ -1235,6 +1313,50 @@ architecture behaviour of ccsds_rxtx_bench is
         wait;
       end process;
     --=============================================================================
+    -- Begin of coderdiffp
+    -- generation of coder differential subsystem unit-tests
+    --=============================================================================
+    -- read: bench_res_coder_diff0_dat, bench_res_coder_diff0_dat_val
+    -- write: bench_ena_coder_diff0_random_data, bench_sti_coder_diff0_dat_val
+    -- r/w: 
+    CODERDIFFP : process
+    begin
+      -- let the system free run
+        wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
+      -- default state tests:
+        if (bench_res_coder_diff0_dat_val = '1') then
+          report "CODERDIFFP: KO - Default state - Differential coder output data is valid" severity warning;
+        else
+          report "CODERDIFFP: OK - Default state - Differential coder output data is not valid" severity note;
+        end if;
+      -- let the system reset
+        wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CODER_DIFF_WAIT_DURATION);
+      -- initial state tests:
+        if (bench_res_coder_diff0_dat_val = '1') then
+          report "CODERDIFFP: KO - Initial state - Differential coder output data is valid" severity warning;
+        else
+          report "CODERDIFFP: OK - Initial state - Differential coder output data is not valid" severity note;
+        end if;
+      -- behaviour tests:
+        report "CODERDIFFP: START DIFFERENTIAL CODER TESTS" severity note;
+        bench_ena_coder_diff0_random_data <= '1';
+        wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
+        bench_sti_coder_diff0_dat_val <= '1';
+        wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD*CCSDS_RXTX_BENCH_CODER_DIFF0_WORDS_NUMBER;
+        bench_sti_coder_diff0_dat_val <= '0';
+        bench_ena_coder_diff0_random_data <= '0';
+        wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
+      -- final state tests:
+        if (bench_res_coder_diff0_dat_val = '1') then
+          report "CODERDIFFP: KO - Final state - Differential coder output data is valid" severity warning;
+        else
+          report "CODERDIFFP: OK - Final state - Differential coder output data is not valid" severity note;
+        end if;
+        report "CODERDIFFP: END DIFFERENTIAL CODER TESTS" severity note;
+      -- do nothing
+        wait;
+    end process;
+    --=============================================================================
     -- Begin of crcp
     -- generation of crc subsystem unit-tests
     --=============================================================================
@@ -1661,15 +1783,34 @@ architecture behaviour of ccsds_rxtx_bench is
       -- let the system free run
         wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
       -- default state tests:
+        if (bench_res_mapper0_sym_val = '1') then
+          report "MAPPERP: KO - Default state - Mapper output data is valid" severity warning;
+        else
+          report "MAPPERP: OK - Default state - Mapper output data is not valid" severity note;
+        end if;
       -- let the system reset
         wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_MAPPER_WAIT_DURATION);
       -- initial state tests:
+        if (bench_res_mapper0_sym_val = '1') then
+          report "MAPPERP: KO - Initial state - Mapper output data is valid" severity warning;
+        else
+          report "MAPPERP: OK - Initial state - Mapper output data is not valid" severity note;
+        end if;
       -- behaviour tests:
         report "MAPPERP: START MAPPER TESTS" severity note;
         bench_ena_mapper0_random_data <= '1';
         wait for CCSDS_RXTX_BENCH_MAPPER0_DATA_CLK_PERIOD;
         bench_sti_mapper0_dat_val <= '1';
+        wait for CCSDS_RXTX_BENCH_MAPPER0_DATA_CLK_PERIOD*CCSDS_RXTX_BENCH_MAPPER0_DATA_BUS_SIZE/CCSDS_RXTX_BENCH_MAPPER0_BITS_PER_SYMBOL*CCSDS_RXTX_BENCH_MAPPER0_WORDS_NUMBER;
+        bench_sti_mapper0_dat_val <= '0';
+        bench_ena_mapper0_random_data <= '0';
+        wait for CCSDS_RXTX_BENCH_MAPPER0_DATA_CLK_PERIOD;
       -- final state tests:
+        if (bench_res_mapper0_sym_val = '1') then
+          report "MAPPERP: KO - Final state - Mapper output data is valid" severity warning;
+        else
+          report "MAPPERP: OK - Final state - Mapper output data is not valid" severity note;
+        end if;
         report "MAPPERP: END MAPPER TESTS" severity note;
       -- do nothing
         wait;
@@ -1956,6 +2097,7 @@ architecture behaviour of ccsds_rxtx_bench is
         report "RESETP: START RESET SIGNAL TEST" severity note;
         -- send reset signals
         bench_sti_rxtx0_wb_rst <= '1';
+        bench_sti_coder_diff0_rst <= '1';
         bench_sti_crc0_rst <= '1';
         bench_sti_buffer0_rst <= '1';
         bench_sti_filter0_rst <= '1';
@@ -1968,6 +2110,7 @@ architecture behaviour of ccsds_rxtx_bench is
         report "RESETP: END RESET SIGNAL TEST" severity note;
         -- stop reset signals
         bench_sti_rxtx0_wb_rst <= '0';
+        bench_sti_coder_diff0_rst <= '0';
         bench_sti_crc0_rst <= '0';
         bench_sti_buffer0_rst <= '0';
         bench_sti_filter0_rst <= '0';

hw/rtl/ccsds_rxtx/ccsds_rxtx_top.vhd

@@ -130,6 +130,7 @@ architecture structure of ccsds_rxtx_top is
         dat_ser_i: in std_logic;
         buf_ful_o: out std_logic;
         clk_o: out std_logic;
+        idl_o: out std_logic;
         sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
         sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
         ena_o: out std_logic
@@ -190,6 +191,7 @@ begin
         dat_ser_i => tx_dat_ser_i,
         buf_ful_o => wire_tx_buf_ful,
         clk_o => tx_clk_o,
+        idl_o => tx_idl_o,
         sam_i_o => tx_sam_i_o,
         sam_q_o => tx_sam_q_o,
         ena_o => tx_ena_o

hw/rtl/ccsds_rxtx/ccsds_tx.vhd

@@ -27,7 +27,7 @@ entity ccsds_tx is
   generic (
     constant CCSDS_TX_BITS_PER_SYMBOL: integer := 1;
     constant CCSDS_TX_BUFFER_SIZE: integer := 16; -- max number of words stored for burst write at full speed when datalinklayer is full
-    constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=QAM/QPSK / 2=GMSK
+    constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=QAM/QPSK / 2=BPSK
     constant CCSDS_TX_DATA_BUS_SIZE: integer;
     constant CCSDS_TX_OVERSAMPLING_RATIO: integer := 4; -- symbols to samples over-sampling ratio
     constant CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
@@ -98,7 +98,8 @@ architecture structure of ccsds_tx is
   end component;
   component ccsds_tx_datalink_layer is
     generic(
-      CCSDS_TX_DATALINK_DATA_BUS_SIZE : integer
+      CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer;
+      CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer
     );
     port(
       clk_bit_i: in std_logic;
@@ -186,7 +187,8 @@ begin
     );
   tx_datalink_layer_0: ccsds_tx_datalink_layer
     generic map(
-      CCSDS_TX_DATALINK_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE
+      CCSDS_TX_DATALINK_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
+      CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_BITS_PER_SYMBOL
     )
     port map(
       clk_dat_i => wire_clk_dat,

hw/rtl/ccsds_rxtx/ccsds_tx_coder.vhd

@@ -25,7 +25,9 @@ use ieee.std_logic_1164.all;
 entity ccsds_tx_coder is
   generic(
     constant CCSDS_TX_CODER_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
-    constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer -- in bits
+    constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer; -- in bits
+    constant CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword (should be equal to bits per symbol of lower link)
+    constant CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean -- Enable differential coder
   );
   port(
     -- inputs
@@ -43,6 +45,20 @@ end ccsds_tx_coder;
 -- architecture declaration / internal components and connections
 --=============================================================================
 architecture structure of ccsds_tx_coder is
+  component ccsds_tx_coder_differential is
+    generic(
+      CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
+      CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
+    );
+    port(
+      clk_i: in std_logic;
+      dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
+      dat_val_i: in std_logic;
+      rst_i: in std_logic;
+      dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
+      dat_val_o: out std_logic
+    );
+  end component;
   component ccsds_tx_randomizer is
     generic(
       CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer
@@ -58,24 +74,26 @@ architecture structure of ccsds_tx_coder is
   end component;
   component ccsds_tx_synchronizer is
     generic(
-      CCSDS_TX_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
-      CCSDS_TX_ASM_DATA_BUS_SIZE: integer -- in bits
+      CCSDS_TX_ASM_LENGTH: integer;
+      CCSDS_TX_ASM_DATA_BUS_SIZE: integer
     );
     port(
-      -- inputs
       clk_i: in std_logic;
       dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
       dat_val_i: in std_logic;
       rst_i: in std_logic;
-      -- outputs
       dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
       dat_val_o: out std_logic
     );
   end component;
 -- internal constants
 -- internal variable signals
+  signal wire_coder_diff_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
+  signal wire_coder_diff_dat_val_o: std_logic;
   signal wire_randomizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
   signal wire_randomizer_dat_val_o: std_logic;
+  signal wire_synchronizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
+  signal wire_synchronizer_dat_val_o: std_logic;
 -- components instanciation and mapping
   begin
   tx_coder_randomizer_0: ccsds_tx_randomizer
@@ -90,19 +108,49 @@ architecture structure of ccsds_tx_coder is
       dat_val_o => wire_randomizer_dat_val_o,
       dat_o => wire_randomizer_dat_o
     );
-  tx_coder_synchronizer_0: ccsds_tx_synchronizer
-    generic map(
-      CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
-      CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
-    )
-    port map(
-      clk_i => clk_i,
-      rst_i => rst_i,
-      dat_val_i => wire_randomizer_dat_val_o,
-      dat_i => wire_randomizer_dat_o,
-      dat_val_o => dat_val_o,
-      dat_o => dat_o
-    );
+  NODIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = false) generate
+    tx_coder_synchronizer_0: ccsds_tx_synchronizer
+      generic map(
+        CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
+        CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
+      )
+      port map(
+        clk_i => clk_i,
+        rst_i => rst_i,
+        dat_val_i => wire_randomizer_dat_val_o,
+        dat_i => wire_randomizer_dat_o,
+        dat_val_o => dat_val_o,
+        dat_o => dat_o
+      );
+   end generate NODIFFCODERGENP;
+  DIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = true) generate
+    tx_coder_synchronizer_0: ccsds_tx_synchronizer
+      generic map(
+        CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
+        CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
+      )
+      port map(
+        clk_i => clk_i,
+        rst_i => rst_i,
+        dat_val_i => wire_randomizer_dat_val_o,
+        dat_i => wire_randomizer_dat_o,
+        dat_val_o => wire_synchronizer_dat_val_o,
+        dat_o => wire_synchronizer_dat_o
+      );
+    tx_coder_differential_0: ccsds_tx_coder_differential
+      generic map(
+        CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
+        CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8
+      )
+      port map(
+        clk_i => clk_i,
+        rst_i => rst_i,
+        dat_val_i => wire_synchronizer_dat_val_o,
+        dat_i => wire_synchronizer_dat_o,
+        dat_val_o => dat_val_o,
+        dat_o => dat_o
+      );
+   end generate DIFFCODERGENP;
 -- presynthesis checks
 -- internal processing
 end structure;

hw/rtl/ccsds_rxtx/ccsds_tx_datalink_layer.vhd

@@ -19,7 +19,6 @@
 -- libraries used
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.math_real.all;
 
 --=============================================================================
 -- Entity declaration for ccsds_tx / unitary tx datalink layer inputs and outputs
@@ -27,7 +26,9 @@ use ieee.math_real.all;
 entity ccsds_tx_datalink_layer is
   generic (
     constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
-    constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer := 32; -- in bits
+    constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
+    constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
+    constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
     constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
     constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
     constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
@@ -71,6 +72,8 @@ architecture structure of ccsds_tx_datalink_layer is
   end component;
   component ccsds_tx_coder is
     generic(
+      CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
+      CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
       CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
       CCSDS_TX_CODER_ASM_LENGTH: integer
     );
@@ -117,7 +120,9 @@ architecture structure of ccsds_tx_datalink_layer is
   tx_datalink_coder_0: ccsds_tx_coder
     generic map(
       CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
-      CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8
+      CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
+      CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
+      CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
     )
     port map(
       clk_i => clk_dat_i,
@@ -127,15 +132,35 @@ architecture structure of ccsds_tx_datalink_layer is
       dat_val_o => wire_coder_data_valid,
       dat_o => wire_coder_data
     );
-
 -- presynthesis checks
 -- internal processing
     --=============================================================================
     -- Begin of bitsoutputp
     -- Generate valid bits output word by word on coder data_valid signal
     --=============================================================================
-    -- read: rst_i, wire_coder_data, wire_coder_data_valid
-    -- write: dat_o, dat_val_o
+    -- read: rst_i, wire_coder_data_valid
+    -- write: dat_val_o
+    -- r/w: 
+    BITSVALIDP: process (clk_dat_i)
+    begin
+      -- on each clock rising edge
+      if rising_edge(clk_dat_i) then
+        -- reset signal received
+        if (rst_i = '1') then
+          dat_val_o <= '0';
+        else
+          if (wire_coder_data_valid = '1') then
+            dat_val_o <= '1';
+          end if;
+        end if;
+      end if;
+    end process;
+    --=============================================================================
+    -- Begin of bitsoutputp
+    -- Generate valid bits output word by word on coder data_valid signal
+    --=============================================================================
+    -- read: rst_i, wire_coder_data
+    -- write: dat_o
     -- r/w: 
     BITSOUTPUTP: process (clk_bit_i)
     variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
@@ -147,16 +172,13 @@ architecture structure of ccsds_tx_datalink_layer is
         if (rst_i = '1') then
           next_word_pointer := FRAME_OUTPUT_WORDS - 1;
           dat_o <= (others => '0');
-          dat_val_o <= '0';
         else
           -- generating valid bits output words
           if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
             current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
             dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
             next_word_pointer := FRAME_OUTPUT_WORDS - 2;
-            dat_val_o <= '1';
           else
-            dat_val_o <= '1';
             dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
             if (next_word_pointer = 0) then
               next_word_pointer := FRAME_OUTPUT_WORDS - 1;

hw/rtl/ccsds_rxtx/ccsds_tx_filter.vhd

@@ -26,7 +26,7 @@ entity ccsds_tx_filter is
   generic(
     constant CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer; -- in bits
     constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
-    constant CCSDS_TX_FILTER_OFFSET_PSK: boolean := true;
+    constant CCSDS_TX_FILTER_OFFSET_IQ: boolean := true;
     constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
     constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer
   );
@@ -128,7 +128,7 @@ architecture structure of ccsds_tx_filter is
     tx_oversampler_q_0: ccsds_rxtx_oversampler
       generic map(
         CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
-        CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_PSK,
+        CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_IQ,
         CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
       )
       port map(

hw/rtl/ccsds_rxtx/ccsds_tx_mapper.vhd

@@ -20,7 +20,6 @@
 -- libraries used
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
 
 --=============================================================================
 -- Entity declaration for ccsds_tx / unitary tx mapper inputs and outputs
@@ -28,7 +27,6 @@ use ieee.numeric_std.all;
 entity ccsds_tx_mapper is
   generic(
     constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer := 1; -- For QAM - 1 bit/symbol <=> QPSK/4-QAM - 2 bits/symbol <=> 16-QAM - 3 bits/symbol <=> 64-QAM - ... - N bits/symbol <=> 2^(N*2)-QAM
-    constant CCSDS_TX_MAPPER_DIFFERENTIAL_CODER: boolean := false; -- Differential coder activation
     constant CCSDS_TX_MAPPER_GRAY_CODER: std_logic := '1'; -- Gray coder activation
     constant CCSDS_TX_MAPPER_MODULATION_TYPE: integer := 1; -- 1=QPSK/QAM - 2=BPSK
     constant CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer -- in bits
@@ -53,8 +51,6 @@ architecture structure of ccsds_tx_mapper is
 -- internal constants
   constant MAPPER_SYMBOL_NUMBER_PER_CHANNEL: integer := CCSDS_TX_MAPPER_DATA_BUS_SIZE*CCSDS_TX_MAPPER_MODULATION_TYPE/(2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
 -- internal variable signals
-  signal symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
-  signal prev_sym: std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0) := (others => '0');
 -- components instanciation and mapping
   begin
 -- presynthesis checks
@@ -88,6 +84,7 @@ architecture structure of ccsds_tx_mapper is
     -- write: sym_i_o, sym_q_o
     -- r/w:
     MAPPERP: process (clk_i)
+    variable symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
     begin
       -- on each clock rising edge
       if rising_edge(clk_i) then
@@ -95,45 +92,24 @@ architecture structure of ccsds_tx_mapper is
         if (rst_i = '1') then
           sym_i_o <= (others => '0');
           sym_q_o <= (others => '0');
-          prev_sym <= (others => '0');
-          symbol_counter <= MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
+          symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
           sym_val_o <= '0';
         else
           if (dat_val_i = '1') then
             sym_val_o <= '1';
-            -- Differential coding
-            if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
-              -- BPSK
-              if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
-                prev_sym <= dat_i(symbol_counter-1 downto symbol_counter-1);
-              -- QPSK/QAM
-              else
-                prev_sym <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-              end if;
-            end if;
             -- BPSK mapping
             if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
               sym_q_o(0) <= '0';
-              if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
-                sym_i_o(0 downto 0) <= dat_i(symbol_counter-1 downto symbol_counter-1) xor prev_sym;
-              else
-                sym_i_o(0) <= dat_i(symbol_counter-1);
-              end if;
+              sym_i_o(0) <= dat_i(symbol_counter-1);
             -- QPSK/QAM mapping
             else
-              if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
---TODO HERE: GRAY MAPPING
-                sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL) xor prev_sym;
-                sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL) xor dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-              else
-                sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-                sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-              end if;
+              sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
+              sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
             end if;
             if (symbol_counter = 1) then
-              symbol_counter <= MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
+              symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
             else
-              symbol_counter <= symbol_counter - 1;
+              symbol_counter := symbol_counter - 1;
             end if;
           else
             sym_val_o <= '0';