Commit 22391118 authored by Guillaume REMBERT's avatar Guillaume REMBERT

Initial commit for hdl files

parent 2d789f2d
-------------------------------
Project: EurySPACE
Version: 1.0.0
Date: 2016/13/03
-------------------------------
Author(s):
Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
-------------------------------
License:
MIT - Please read LICENSE file for more information
-------------------------------
-------------------------------
README INDEX
-------------------------------
0 - Project Presentation
-------------------------------
This section presents the EurySPACE project.
Start first by reading these lines.
-------------------------------
1 - Repository Structure
-------------------------------
This section presents the repository structure.
Read these lines to understand the files layout.
-------------------------------
2: Integration Methodology
-------------------------------
This section presents a methodology to be used to integrate the solution.
Read these lines to check and/or define your integration plan.
-------------------------------
3: Development Guidelines
-------------------------------
This section presents coding style conventions.
Read these lines to modify and/or extend the system.
-------------------------------
4: Quick Start
-------------------------------
This section summarizes what is needed to setup and run the solution.
Read these lines to build, install and start the system.
-------------------------------
-------------------------------
PART 0 - PROJECT PRESENTATION
-------------------------------
FIXME: TBD / Features, supported platforms, etc
-------------------------------
-------------------------------
PART 1 - REPOSITORY STRUCTURE
-------------------------------
\ cfg (ConFiGuration): configuration files
-------------------------------
\ hw (HardWare): TBD
\ sw (SoftWare): TBD
-------------------------------
\ doc (DOCumentation): documentation
-------------------------------
\ ddd (Detailed Design Document): architecture, algorithms and design details
\ icd (Interface Control Document): API, internal and external files formats description
\ trp (Test RePorts): stable releases test reports
\ ugd (User GuiDe): installation, configuration and use guide
-------------------------------
\ gis (Geographical Information System): GIS data
-------------------------------
\ gml (Geographical Markup Language): TBD
\ shp (SHaPe Files): TBD
-------------------------------
\ hw (HardWare): hardware data
-------------------------------
\ bom (Bill Of Materials)
\ cad (Computer Aided Design)
\ dts (DaTaSheets)
\ grb (GeRBers)
\ rtl (Register Transfer Level)
\ ccsds_rxtx (CCSDS Receiver-Emitter)
\ euryspace_soc (EURYSPACE System On Chip)
----
apm = Analog Processing Module
dpm = Digital Processing Module
iui = Information Universe Interface
-------------------------------
\ sim (SIMulation): simulation tools and data-sets
-------------------------------
\ dat (raw DATa)
\ grc (GnuRadio Companion)
\ oct (OCTave)
\ qemu (QEMU)
\ smp (SaMPles)
-------------------------------
\ sw (SoftWare): software data
-------------------------------
\ bin (BINaries): qualified binaries
\ RELEASE_VERSION_X.XX.XX
\ SOFTWARE_NAME-or1k_X.XX.XX-gcc_X.XX.XX-newlib_X.XX.XX
\ pkg (PacKaGes): platform specific installation packages
\ RELEASE_VERSION_X.XX.XX
\ SOFTWARE_NAME
\ apk: Android
\ bsd: BSD Unix
\ deb: Debian/Ubuntu Linux
\ ios: iOS
\ rpm: RedHat/CentOS/Fedora/OpenSUSE Linux
\ win: Windows
\ src (SouRCes): software source code
\ ground_segment
\ core
\ control
\ display
\ emission
\ process
\ reception
\ space_segment
\ core
\ control
\ emission
\ reception
\ application
\ localisation
\ observation
\ telecommunication
\ user_segment
\ core
\ display
\ emission
\ reception
\ application
\ localisation
\ observation
\ telecommunication
\ euryspace_test_center
\ calibration
\ emission
\ reception
-------------------------------
\ tst (TeST): test tools and data-sets
-------------------------------
\ rtl
\ ccsds_rxtx_bench
\ euryspace_soc_bench
\ sh (SHell)
\ euryspace_auto_calibration
\ euryspace_auto_test
-------------------------------
-------------------------------
PART 2: INTEGRATION METHODOLOGY
-------------------------------
FIXME: TBD / Specs -> Design -> Code -> Test
-------------------------------
-------------------------------
PART 3: DEVELOPMENT GUIDELINES
-------------------------------
FIXME: TBD / variables / functions / comments / ...
-------------------------------
-------------------------------
PART 4: QUICK START
-------------------------------
FIXME: TBD / HW and SW requirements, OS setup, build, install, test
-------------------------------
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rx
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary rx external physical inputs and outputs
entity ccsds_rx is
generic (
CCSDS_RX_PHYS_SIG_QUANT_DEPTH : integer := 16;
CCSDS_RX_DATA_OUTPUT_TYPE: integer := 0;
CCSDS_RX_DATA_INPUT_TYPE: integer := 0;
CCSDS_RX_DATA_BUS_SIZE: integer := 32
);
port(
rst_i: in std_logic; -- system reset input
ena_i: in std_logic; -- system enable input
clk_i: in std_logic; -- input samples clock
i_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
q_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
if_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- intermediate frequency real parallel samples
i_samples_ser_i: in std_logic; -- in-phased serial complex samples
q_samples_ser_i: in std_logic; -- quadrature-phased serial complex samples
if_samples_ser_i: in std_logic; -- intermediate-frequency serial real samples
clk_o: out std_logic; -- received data clock
data_par_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
data_ser_o: out std_logic -- received data serial output
);
end ccsds_rx;
architecture structure of ccsds_rx is
component ccsds_rx_datalink_layer is
generic(
CCSDS_RX_DATALINK_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
);
end component;
component ccsds_rx_physical_layer is
generic(
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH : integer;
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
i_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
q_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
if_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
i_samples_ser_i: in std_logic;
q_samples_ser_i: in std_logic;
if_samples_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
);
end component;
signal wire_data_par: std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
signal wire_data_ser: std_logic;
signal wire_clk_m: std_logic;
signal wire_clk_i: std_logic;
begin
rx_datalink_layer_1: ccsds_rx_datalink_layer
generic map(
CCSDS_RX_DATALINK_DATA_BUS_SIZE => CCSDS_RX_DATA_BUS_SIZE
)
port map(
clk_i => wire_clk_m,
clk_o => clk_o,
rst_i => rst_i,
data_par_i => wire_data_par,
data_ser_i => wire_data_ser,
data_par_o => data_par_o,
data_ser_o => data_ser_o
);
rx_physical_layer_1: ccsds_rx_physical_layer
generic map(
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH => CCSDS_RX_PHYS_SIG_QUANT_DEPTH,
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE => CCSDS_RX_DATA_BUS_SIZE
)
port map(
clk_i => wire_clk_i,
clk_o => wire_clk_m,
rst_i => rst_i,
i_samples_par_i => i_samples_par_i,
q_samples_par_i => q_samples_par_i,
if_samples_par_i => if_samples_par_i,
i_samples_ser_i => i_samples_ser_i,
q_samples_ser_i => q_samples_ser_i,
if_samples_ser_i => if_samples_ser_i,
data_par_o => wire_data_par,
data_ser_o => wire_data_ser
);
--=============================================================================
-- Begin of enablep
-- Enable/disable clk forwarding
--=============================================================================
-- read: clk_i, ena_i
-- write: wire_clk_i
-- r/w:
ENABLEP : process (clk_i, ena_i)
begin
if (ena_i = '1') then
wire_clk_i <= clk_i;
else
wire_clk_i <= '0';
end if;
end process;
end structure;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rx_datalink_layer
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary rx datalink layer
entity ccsds_rx_datalink_layer is
generic (
CCSDS_RX_DATALINK_DATA_BUS_SIZE: integer := 32
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
);
end ccsds_rx_datalink_layer;
-- internal processing
architecture rtl of ccsds_rx_datalink_layer is
begin
-- TEMPORARY NO CHANGE / DUMMY LINKLAYER
DATALINKP : process (clk_i, data_par_i, data_ser_i)
begin
data_par_o <= data_par_i;
data_ser_o <= data_ser_i;
clk_o <= clk_i;
end process;
end rtl;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rx_physical_layer
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_rx_physical_layer / unitary rx physical layer
--=============================================================================
entity ccsds_rx_physical_layer is
generic (
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH : integer := 16;
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE: integer := 32
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
i_samples_par_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
q_samples_par_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
if_samples_par_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
i_samples_ser_i: in std_logic;
q_samples_ser_i: in std_logic;
if_samples_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
);
end ccsds_rx_physical_layer;
--=============================================================================
-- architecture declaration / internal processing
--=============================================================================
architecture rtl of ccsds_rx_physical_layer is
--=============================================================================
-- architecture begin
--=============================================================================
begin
--=============================================================================
-- Begin of physicalp
-- TEST PURPOSES / DUMMY PHYSICAL LAYER PROCESS
--=============================================================================
-- read: clk_i
-- write:
-- r/w:
PHYSICALP : process (clk_i, i_samples_par_i, q_samples_par_i, if_samples_par_i, i_samples_ser_i, q_samples_ser_i, if_samples_ser_i)
begin
data_par_o(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH) <= q_samples_par_i;
data_par_o(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0) <= i_samples_par_i;
data_ser_o <= i_samples_ser_i;
clk_o <= clk_i;
end process;
end rtl;
--=============================================================================
-- architecture end
--=============================================================================
CAPI=1
[main]
description = EurySPACE CCSDS RX/TX with wishbone interface
[vhdl]
src_files =
ccsds_rxtx_bench.vhd
ccsds_rxtx_top.vhd
ccsds_rxtx_constants.vhd
ccsds_rxtx_functions.vhd
ccsds_rxtx_parameters.vhd
# ccsds_rxtx_serdes.vhd
ccsds_rxtx_buffer.vhd
ccsds_rx.vhd
ccsds_rx_datalink_layer.vhd
ccsds_rx_physical_layer.vhd
ccsds_tx.vhd
ccsds_tx_datalink_layer.vhd
ccsds_tx_physical_layer.vhd
ccsds_tx_framer.vhd
ccsds_tx_header.vhd
ccsds_tx_trailer.vhd
# ccsds_rxtx_layer_1.vhdl
# ccsds_rxtx_layer_2.vhdl
# ccsds_rxtx_codec_ecc_crc.vhdl
# ccsds_rxtx_codec_ecc_reed_solomon.vhdl
# ccsds_rxtx_codec_ecc_conv_codes.vhdl
# ccsds_rxtx_mapper_gray.vhdl
# ccsds_rxtx_mapper_psk.vhdl
# ccsds_rxtx_mapper_qam.vhdl
# ccsds_rxtx_modulator.vhdl
# ccsds_rxtx_demodulator.vhdl
# ccsds_rxtx_filter_rrc.vhdl
# ccsds_rxtx_estim_symbol_timing.vhdl
# ccsds_rxtx_estim_phase.vhdl
# ccsds_rxtx_filter_rrc.vhdl
This diff is collapsed.
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_buffer
---- Version: 1.0.0
---- Description:
---- Simple FIFO circular buffer
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary rxtx buffer
entity ccsds_rxtx_buffer is
generic(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer := 32;
CCSDS_RXTX_BUFFER_SIZE : integer range 2 to 100000 := 256
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
buf_empty_o: out std_logic;
buf_full_o: out std_logic;
next_data_i: in std_logic;
data_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
data_valid_i: in std_logic;
data_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
data_valid_o: out std_logic
);
end ccsds_rxtx_buffer;
architecture rtl of ccsds_rxtx_buffer is
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := CCSDS_RXTX_BUFFER_SIZE-1;
signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
signal buffer_full: std_logic := '0';
signal buffer_empty: std_logic := '1';
type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE-1 downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
signal buffer_data: buffer_array;
begin
BUFFERSTATEP : process (clk_i)
-- variable previous_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
--variable previous_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
if (rst_i = '0') then
buffer_full <= '0';
buffer_empty <= '1';
else
if (buffer_write_pos = buffer_read_pos) then
buffer_full <= '1';
buffer_empty <= '0';
else
buffer_full <= '0';
end if;
if (buffer_full = '0') then
if (buffer_read_pos+1 = CCSDS_RXTX_BUFFER_SIZE) then
if (buffer_write_pos = 0) then
buffer_empty <= '1';
else
buffer_empty <= '0';
end if;
else
if (buffer_read_pos+1 = buffer_write_pos) then
buffer_empty <= '1';
else
buffer_empty <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
-- PUSH - WRITE OPERATIONS
BUFFERPUSH : process (clk_i)
variable push_state: std_logic := '0';
begin
if rising_edge(clk_i) then
if (rst_i = '0') then
push_state := '0';
buffer_write_pos <= 0;
else
-- check if buffer is full
if (buffer_full = '0') and (data_valid_i = '1') and (push_state = '0') then
-- copy data to buffer mem
buffer_data(buffer_write_pos) <= data_i;
push_state := '1';
--end of circular buffer is reached
if (buffer_write_pos+1 = CCSDS_RXTX_BUFFER_SIZE) then
buffer_write_pos <= 0;
else
buffer_write_pos <= buffer_write_pos + 1;
end if;
else
push_state := '0';
end if;
end if;
end if;
end process;
-- PULL - READ OPERATIONS
BUFFERPULLP : process (clk_i)
variable pull_state: std_logic := '0';
begin
if rising_edge(clk_i) then
if (rst_i = '0') then
pull_state := '0';
buffer_read_pos <= CCSDS_RXTX_BUFFER_SIZE-1;
else
-- check if buffer is empty
if (buffer_empty = '0') and (next_data_i = '1') and (pull_state = '0') then
data_valid_o <= '1';
pull_state := '1';
if ((buffer_read_pos + 1) = CCSDS_RXTX_BUFFER_SIZE) then
buffer_read_pos <= 0;
else
buffer_read_pos <= buffer_read_pos + 1;
end if;
else
pull_state := '0';
data_valid_o <= '0';
end if;
end if;
end if;
end process;
buf_empty_o <= buffer_empty;
buf_full_o <= buffer_full;
data_o <= buffer_data(buffer_read_pos);
clk_o <= clk_i;
end rtl;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_constants
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert , guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
package ccsds_rxtx_constants is
constant TX_OK: integer := 1; -- datalink ok
end ccsds_rxtx_constants;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_functions
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert , guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/12/28: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package ccsds_rxtx_functions is
-- simulation : testbench only functions
procedure simGetRandomBitVector(vectorSize : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
-- synthetizable functions
end ccsds_rxtx_functions;
package body ccsds_rxtx_functions is
procedure simGetRandomBitVector(vectorSize : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector) is
variable rand : real := 0.0;
begin
-- report "DEBUG: Seeds values => seed1 = " & positive'image(seed1) & " seed2 = " & positive'image(seed2) severity warning;
uniform(seed1, seed2, rand);
-- report "DEBUG: Random value => rand = " & real'image(rand) severity warning;
-- report "DEBUG: Seeds values => seed1 = " & positive'image(seed1) & " seed2 = " & positive'image(seed2) severity warning;
rand := rand*(2**(real(vectorSize)-1.0));
-- report "DEBUG: Random value => rand = " & real'image(rand) severity warning;
result := std_logic_vector(to_unsigned(integer(rand),vectorSize));
end simGetRandomBitVector;
end ccsds_rxtx_functions;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_parameters
---- Version: 1.0.0
---- Description:
---- Project / design specific parameters
-------------------------------
---- Author(s):
---- Guillaume Rembert , guillaume.rembert@euryecetelecom.com
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
package ccsds_rxtx_parameters is
-- SYSTEM CONFIGURATION
constant RXTX_SYSTEM_WB_DATA_BUS_SIZE: integer := 32;-- Wishbone slave data bus size
constant RXTX_SYSTEM_WB_ADDR_BUS_SIZE: integer := 4;-- Wishbone slave address bus size
-- RX CONFIGURATION
constant RX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of RX at startup
constant RX_SYSTEM_AUTO_EXTERNAL: std_logic := '0';--Automatic configuration of RX to use external clock and data
constant RX_SYSTEM_DATA_BUS_SIZE: integer := 32;-- RX parallel input data bus size
constant RX_SYSTEM_DATA_INPUT_TYPE: integer := 0;-- RX ext samples input type (0=serial i&q, 1=serial if, 2=parallel i&Q, 3=parallel if)
constant RX_SYSTEM_DATA_OUTPUT_TYPE: integer := 0;-- RX ext data output type (0=serial, 1=parallel)
constant RX_SYSTEM_DATA_DEFAULT_DATA: std_logic_vector(31 downto 0) := "01000000000000000000000000000010";
-- TX CONFIGURATION
constant TX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of TX at startup
constant TX_SYSTEM_AUTO_EXTERNAL: std_logic := '0';--Automatic configuration of RX to use external clock and data
constant TX_SYSTEM_DATA_BUS_SIZE: integer := 32;-- TX parallel input data bus size (bits)
constant TX_SYSTEM_DATA_BUFFER_SIZE: integer := 256;--TX parallel input data words buffer size (words of TX_SYSTEM_DATA_BUS_SIZE bits)
constant TX_SYSTEM_DATA_INPUT_TYPE: integer := 0;-- TX ext input data type (0=serial, 1=parallel)
constant TX_SYSTEM_DATA_OUTPUT_TYPE: integer := 0;-- TX ext output samples type (0= serial i&q, 1=serial if, 2=parallel i&Q, 3=parallel if)
constant TX_SYSTEM_DATA_DEFAULT_DATA: std_logic_vector(31 downto 0) := (others => '1');
-- LAYERS CONFIGURATION
-- APPLICATION LAYER
-- PRESENTATION LAYER