Commit 22a33b4d authored by Guillaume REMBERT's avatar Guillaume REMBERT

Symbols to samples mapper + bits to symbols mapper + differential coder file

parent 48e03628
......@@ -28,7 +28,8 @@ files =
ccsds_tx_framer.vhd
ccsds_tx_header.vhd
ccsds_tx_manager.vhd
ccsds_tx_mapper.vhd
ccsds_tx_mapper_bits_symbols.vhd
ccsds_tx_mapper_symbols_samples.vhd
ccsds_tx_physical_layer.vhd
ccsds_tx_randomizer.vhd
ccsds_tx_synchronizer.vhd
......
This diff is collapsed.
......@@ -56,17 +56,17 @@ package body ccsds_rxtx_functions is
variable rand: real := 0.0;
variable temp: std_logic_vector(31 downto 0);
begin
if (vector_size <= 32) then
if (vector_size < 32) then
uniform(seed1, seed2, rand);
rand := rand*(2**(real(vector_size)-1.0));
rand := rand*(2**(real(vector_size))-1.0);
result := std_logic_vector(to_unsigned(integer(rand),vector_size));
else
uniform(seed1, seed2, rand);
for vector_pointer in 0 to vector_size-1 loop
uniform(seed1, seed2, rand);
rand := rand*(2**(real(32)-1.0));
rand := rand*(2**(real(31))-1.0);
temp := std_logic_vector(to_unsigned(integer(rand),32));
result(vector_pointer) := temp(vector_pointer mod 32);
result(vector_pointer) := temp(0);
end loop;
end if;
end sim_generate_random_std_logic_vector;
......
......@@ -61,7 +61,7 @@ architecture structure of ccsds_rxtx_srrc is
-- internal constants
constant CCSDS_RXTX_SRRC_RESPONSE_SYMBOL_CYCLES: integer:= 6; -- in symbol Time
constant CCSDS_RXTX_SRRC_FIR_COEFFICIENTS_NUMBER: integer := CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO*CCSDS_RXTX_SRRC_RESPONSE_SYMBOL_CYCLES*2+1;
constant CCSDS_RXTX_SRRC_NORMALIZATION_GAIN: real := real(2**(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-2)); -- Exact value should be Sqrt(Sum(Pow(coef,2))) * Full Scale Value
constant CCSDS_RXTX_SRRC_NORMALIZATION_GAIN: real := 2.0**(real(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH) - real(CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO)**0.5 + 1.0) - 1.0; -- Exact value should be (RMS Gain = Sqrt(Sum(Pow(coef,2)))) * Full Scale Value
constant CCSDS_RXTX_SRRC_SIG_MUL_SIZE: integer := 2*CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH;
constant CCSDS_RXTX_SRRC_SIG_ADD_SIZE: integer := CCSDS_RXTX_SRRC_SIG_MUL_SIZE;
-- internal variable signals
......
---- Design Name: ccsds_tx_coder_differential
---- Version: 1.0.0
---- Description:
---- Word by word differential coder
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx mapper inputs and outputs
--=============================================================================
entity ccsds_tx_coder_differential is
generic(
constant CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
constant CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_coder_differential;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_coder_differential is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKCODERP0 : if (CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE mod (CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) /= 0) generate
process
begin
report "ERROR: DATA BUS SIZE HAS TO BE A MULTIPLE OF BITS PER CODE WORD" severity failure;
wait;
end process;
end generate CHKCODERP0;
-- internal processing
--=============================================================================
-- Begin of coderdiffp
-- Differential encode words
--=============================================================================
-- read: rst_i, dat_i, dat_val_i
-- write: dat_o, dat_val_o
-- r/w:
CODERDIFFP: process (clk_i)
variable prev_sym: std_logic_vector(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
dat_val_o <= '0';
prev_sym := (others => '0');
else
if (dat_val_i = '1') then
dat_val_o <= '1';
dat_o(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) <= prev_sym xor dat_i(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD);
for i in CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE/(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD)-1 downto 1 loop
dat_o(i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto (i-1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) <= dat_i(i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto (i-1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD) xor dat_i((i+1)*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto i*CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD);
end loop;
prev_sym := dat_i(CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD-1 downto 0);
else
dat_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
......@@ -157,7 +157,7 @@ architecture structure of ccsds_tx_datalink_layer is
end process;
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
-- Generate bits output word by word based on coder output
--=============================================================================
-- read: rst_i, wire_coder_data
-- write: dat_o
......
......@@ -28,7 +28,8 @@ entity ccsds_tx_filter is
constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_FILTER_OFFSET_IQ: boolean := true;
constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer
constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
constant CCSDS_TX_FILTER_TARGET_SNR: real := 40.0
);
port(
-- inputs
......@@ -48,6 +49,21 @@ end ccsds_tx_filter;
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_filter is
component ccsds_tx_mapper_symbols_samples is
generic(
constant CCSDS_TX_MAPPER_TARGET_SNR: real;
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer;
constant CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
sam_val_o: out std_logic;
sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
);
end component;
component ccsds_rxtx_oversampler is
generic(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer;
......@@ -91,10 +107,24 @@ architecture structure of ccsds_tx_filter is
signal wire_sam_q_srrc_val: std_logic;
-- components instanciation and mapping
begin
tx_mapper_symbols_samples_i_0: ccsds_tx_mapper_symbols_samples
generic map(
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH,
CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_TX_FILTER_TARGET_SNR,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_FILTER_BITS_PER_SYMBOL
)
port map(
clk_i => clk_i,
sym_i => sym_i_i,
sym_val_i => sym_val_i,
rst_i => rst_i,
sam_o => wire_sam_i,
sam_val_o => wire_sam_i_val
);
tx_oversampler_i_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => false,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_IQ,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
......@@ -125,10 +155,24 @@ architecture structure of ccsds_tx_filter is
end generate BPSK_GENERATION;
-- nPSK
NPSK_GENERATION: if (CCSDS_TX_FILTER_MODULATION_TYPE /= 2) or (CCSDS_TX_FILTER_BITS_PER_SYMBOL /= 1) generate
tx_mapper_symbols_samples_q_0: ccsds_tx_mapper_symbols_samples
generic map(
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH,
CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_TX_FILTER_TARGET_SNR,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_FILTER_BITS_PER_SYMBOL
)
port map(
clk_i => clk_i,
sym_i => sym_q_i,
sym_val_i => sym_val_i,
rst_i => rst_i,
sam_o => wire_sam_q,
sam_val_o => wire_sam_q_val
);
tx_oversampler_q_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_IQ,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => false,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
......@@ -163,53 +207,4 @@ architecture structure of ccsds_tx_filter is
wait;
end process;
end generate CHKFILTERP0;
-- internal processing
--=============================================================================
-- Begin of samplesp
-- Convert symbols to signed samples
--=============================================================================
-- read: rst_i, sym_i, sym_val_i
-- write: wire_sam_i, wire_sam_i_val, wire_sam_q, wire_sam_q_val
-- r/w:
SAMPLESP: process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
wire_sam_i_val <= '0';
wire_sam_q_val <= '0';
else
if (sym_val_i = '1') then
wire_sam_i_val <= '1';
wire_sam_q_val <= '1';
if (CCSDS_TX_FILTER_BITS_PER_SYMBOL > 1) then
wire_sam_i(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-2 downto CCSDS_TX_FILTER_SIG_QUANT_DEPTH-CCSDS_TX_FILTER_BITS_PER_SYMBOL) <= sym_i_i(CCSDS_TX_FILTER_BITS_PER_SYMBOL-2 downto 0);
wire_sam_q(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-2 downto CCSDS_TX_FILTER_SIG_QUANT_DEPTH-CCSDS_TX_FILTER_BITS_PER_SYMBOL) <= sym_q_i(CCSDS_TX_FILTER_BITS_PER_SYMBOL-2 downto 0);
end if;
-- positive I value
if (sym_i_i(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1) = '1') then
wire_sam_i(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1) <= '0';
wire_sam_i(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0) <= (others => '1');
--negative I value
else
wire_sam_i(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1) <= '1';
wire_sam_i(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0) <= (others => '0');
end if;
-- positive Q value
if (sym_q_i(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1) = '1') then
wire_sam_q(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1) <= '0';
wire_sam_q(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0) <= (others => '1');
-- negative Q value
else
wire_sam_q(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1) <= '1';
wire_sam_q(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0) <= (others => '0');
end if;
else
wire_sam_i_val <= '0';
wire_sam_q_val <= '0';
end if;
end if;
end if;
end process;
end structure;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_mapper_bits_symbols
---- Version: 1.0.0
---- Description:
---- Map input bits to complex I&Q symbols depending on modulation type
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx bits to symbols mapper inputs and outputs
--=============================================================================
entity ccsds_tx_mapper_bits_symbols is
generic(
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer := 1; -- For QAM - 1 bit/symbol <=> QPSK/4-QAM - 2 bits/symbol <=> 16-QAM - 3 bits/symbol <=> 64-QAM - ... - N bits/symbol <=> 2^(N*2)-QAM
constant CCSDS_TX_MAPPER_GRAY_CODER: std_logic := '1'; -- Gray coder activation
constant CCSDS_TX_MAPPER_MODULATION_TYPE: integer := 1; -- 1=QPSK/QAM - 2=BPSK
constant CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_MAPPER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
sym_val_o: out std_logic;
sym_i_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_q_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0)
);
end ccsds_tx_mapper_bits_symbols;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_mapper_bits_symbols is
-- internal constants
constant MAPPER_SYMBOL_NUMBER_PER_CHANNEL: integer := CCSDS_TX_MAPPER_DATA_BUS_SIZE*CCSDS_TX_MAPPER_MODULATION_TYPE/(2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKMAPPERP0 : if (CCSDS_TX_MAPPER_DATA_BUS_SIZE mod (CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2*CCSDS_TX_MAPPER_MODULATION_TYPE) /= 0) generate
process
begin
report "ERROR: DATA BUS SIZE HAS TO BE A MULTIPLE OF 2*BITS PER SYMBOLS (EXCEPT FOR BPSK MODULATION)" severity failure;
wait;
end process;
end generate CHKMAPPERP0;
CHKMAPPERP1: if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL /= 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) generate
process
begin
report "ERROR: BPSK MODULATION REQUIRES 1 BIT PER SYMBOL" severity failure;
wait;
end process;
end generate CHKMAPPERP1;
CHKMAPPERP2 : if (CCSDS_TX_MAPPER_MODULATION_TYPE /= 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE /= 2) generate
process
begin
report "ERROR: UNKNOWN MODULATION TYPE - 1=QPSK/QAM / 2=BPSK" severity failure;
wait;
end process;
end generate CHKMAPPERP2;
-- internal processing
--=============================================================================
-- Begin of mapperp
-- Map bits to symbols
--=============================================================================
-- read: rst_i, dat_i, dat_val_i
-- write: sym_i_o, sym_q_o, sym_val_o
-- r/w:
MAPPERP: process (clk_i)
variable symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sym_i_o <= (others => '0');
sym_q_o <= (others => '0');
symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
sym_val_o <= '0';
else
if (dat_val_i = '1') then
sym_val_o <= '1';
-- BPSK mapping
if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
sym_q_o(0) <= '0';
sym_i_o(0) <= dat_i(symbol_counter-1);
-- QPSK/QAM mapping
else
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
if (symbol_counter = 1) then
symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
else
symbol_counter := symbol_counter - 1;
end if;
else
sym_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_mapper_symbols_samples
---- Version: 1.0.0
---- Description:
---- Map symbols to their sample value depending on quantization depth
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx bits to symbols mapper inputs and outputs
--=============================================================================
entity ccsds_tx_mapper_symbols_samples is
generic(
constant CCSDS_TX_MAPPER_TARGET_SNR: real; -- in dB
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer; -- in bits
constant CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
-- outputs
sam_val_o: out std_logic;
sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
);
end ccsds_tx_mapper_symbols_samples;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_tx_mapper_symbols_samples is
-- internal constants
constant QUANTIZATION_SNR: real := 6.02*real(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH);
constant REQUIRED_SNR: real := real(2 + 2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL) + CCSDS_TX_MAPPER_TARGET_SNR;
constant SYMBOL_STEP: real := real(2**(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-CCSDS_TX_MAPPER_BITS_PER_SYMBOL)-1);
-- internal variable signals
type samples_array is array(2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL)-1 downto 0) of std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0);
signal symbols_values: samples_array;
-- components instanciation and mapping
begin
SYMBOLS_VALUES_GENERATOR: for symbol_counter in 0 to 2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1)-1 generate
symbols_values(2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1)+symbol_counter) <= std_logic_vector(to_signed(integer(real(symbol_counter+1) * SYMBOL_STEP),CCSDS_TX_MAPPER_QUANTIZATION_DEPTH));
symbols_values(2**(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1)-symbol_counter-1) <= std_logic_vector(to_signed(integer(-(1.0) * real(symbol_counter+1) * SYMBOL_STEP),CCSDS_TX_MAPPER_QUANTIZATION_DEPTH));
end generate SYMBOLS_VALUES_GENERATOR;
-- presynthesis checks
-- Check SNR level requested is respected
-- Signal SNR > crest factor modulated signal + SNR requested from configuration
-- QAMCrestFactor, dB # 2 + 2 * NumberOfBitsPerSymbol
-- QuantizedSignal SNR, dB # 6.02 * QuantizationDepth
CHKMAPPERP0 : if (QUANTIZATION_SNR < REQUIRED_SNR) generate
process
begin
report "ERROR: INCREASE QUANTIZATION DEPTH - QUANTIZATION SNR = " & real'image(QUANTIZATION_SNR) & " dB - REQUIRED SNR = " & real'image(REQUIRED_SNR) severity failure;
wait;
end process;
end generate CHKMAPPERP0;
-- internal processing
--=============================================================================
-- Begin of mapperp
-- Map symbols to samples
--=============================================================================
-- read: rst_i, sym_i, sym_val_i
-- write: sam_val_o, sam_o
-- r/w:
MAPPERP: process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sam_o <= (others => '0');
sam_val_o <= '0';
else
if (sym_val_i = '1') then
sam_o <= symbols_values(to_integer(unsigned(sym_i)));
sam_val_o <= '1';
else
sam_val_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
......@@ -3,7 +3,7 @@
---- Design Name: ccsds_tx_physical_layer
---- Version: 1.0.0
---- Description:
---- CCSDS TX physical layer
---- Implementation of standard CCSDS 401.0-B
-------------------------------
---- Author(s):
---- Guillaume REMBERT
......@@ -14,6 +14,7 @@
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
--TODO: Gray coder
-- libraries used
library ieee;
......@@ -42,8 +43,8 @@ entity ccsds_tx_physical_layer is
end ccsds_tx_physical_layer;
-- internal processing
architecture rtl of ccsds_tx_physical_layer is
component ccsds_tx_mapper is
architecture structure of ccsds_tx_physical_layer is
component ccsds_tx_mapper_bits_symbols is
generic(
CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer;
CCSDS_TX_MAPPER_MODULATION_TYPE: integer;
......@@ -81,10 +82,9 @@ architecture rtl of ccsds_tx_physical_layer is
signal wire_sym_i: std_logic_vector(CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL-1 downto 0);
signal wire_sym_q: std_logic_vector(CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL-1 downto 0);
signal wire_sym_val: std_logic;
signal wire_sam_val: std_logic;
begin
tx_mapper_0: ccsds_tx_mapper
tx_mapper_bits_symbols_0: ccsds_tx_mapper_bits_symbols
generic map(
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL,
CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_TX_PHYSICAL_MODULATION_TYPE,
......@@ -112,8 +112,8 @@ architecture rtl of ccsds_tx_physical_layer is
sym_q_i => wire_sym_q,
sym_val_i => wire_sym_val,
rst_i => rst_i,
sam_val_o => wire_sam_val,
-- sam_val_o => ,
sam_i_o => sam_i_o,
sam_q_o => sam_q_o
);
end rtl;
end structure;
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