Commit 46452972 authored by Guillaume REMBERT's avatar Guillaume REMBERT

Multi-rate management + physical layer implementation: symbol mapper +...

Multi-rate management + physical layer implementation: symbol mapper + oversampler + SRRC fir filter
parent b13a8fc0
......@@ -6,12 +6,15 @@ simulators = ghdl
[fileset rtl_files]
files =
ccsds_rxtx_buffer.vhd
ccsds_rxtx_clock_divider.vhd
ccsds_rxtx_constants.vhd
ccsds_rxtx_crc.vhd
ccsds_rxtx_functions.vhd
ccsds_rxtx_lfsr.vhd
ccsds_rxtx_oversampler.vhd
ccsds_rxtx_parameters.vhd
ccsds_rxtx_serdes.vhd
ccsds_rxtx_srrc.vhd
ccsds_rxtx_top.vhd
ccsds_rx.vhd
ccsds_rx_datalink_layer.vhd
......@@ -19,10 +22,12 @@ files =
ccsds_tx.vhd
ccsds_tx_coder.vhd
ccsds_tx_datalink_layer.vhd
ccsds_tx_filter.vhd
ccsds_tx_footer.vhd
ccsds_tx_framer.vhd
ccsds_tx_header.vhd
ccsds_tx_manager.vhd
ccsds_tx_mapper.vhd
ccsds_tx_physical_layer.vhd
ccsds_tx_randomizer.vhd
ccsds_tx_synchronizer.vhd
......
This diff is collapsed.
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_clock_divider
---- Version: 1.0.0
---- Description:
---- Generate output clock = input clock / divider
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx clock generator inputs and outputs
--=============================================================================
entity ccsds_rxtx_clock_divider is
generic(
constant CCSDS_RXTX_CLOCK_DIVIDER: integer range 1 to 4096
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
-- outputs
clk_o: out std_logic
);
end ccsds_rxtx_clock_divider;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_rxtx_clock_divider is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKCLKDIV0: if (CCSDS_RXTX_CLOCK_DIVIDER mod 2 /= 0) and (CCSDS_RXTX_CLOCK_DIVIDER /= 1) generate
process
begin
report "ERROR: CLOCK DIVIDER MUST BE A MULTIPLE OF 2 OR 1" severity failure;
wait;
end process;
end generate CHKCLKDIV0;
-- internal processing
CLOCKDIVIDER1P: if (CCSDS_RXTX_CLOCK_DIVIDER = 1) generate
clk_o <= clk_i and (not rst_i);
end generate CLOCKDIVIDER1P;
CLOCKDIVIDERNP: if (CCSDS_RXTX_CLOCK_DIVIDER /= 1) generate
--=============================================================================
-- Begin of clockdividerp
-- Clock divider
--=============================================================================
-- read: rst_i
-- write: clk_o
-- r/w:
CLOCKDIVIDERP : process (clk_i, rst_i)
-- variables instantiation
variable counter: integer range 0 to CCSDS_RXTX_CLOCK_DIVIDER/2-1 := CCSDS_RXTX_CLOCK_DIVIDER/2-1;
variable clock_state: std_logic := '1';
begin
if (rst_i = '1') then
clk_o <= '0';
clock_state := '1';
counter := CCSDS_RXTX_CLOCK_DIVIDER/2-1;
else
-- on each clock rising edge
if rising_edge(clk_i) then
clk_o <= clock_state;
if (counter = 0) then
clock_state := clock_state xor '1';
counter := CCSDS_RXTX_CLOCK_DIVIDER/2-1;
else
counter := counter-1;
end if;
end if;
end if;
end process;
end generate CLOCKDIVIDERNP;
end structure;
......@@ -204,6 +204,17 @@ entity ccsds_rxtx_crc is
dat_o: out std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
-- implement input/output registers
attribute useioff: boolean;
attribute useioff of dat_i: signal is true;
attribute useioff of pad_dat_i: signal is true;
attribute useioff of dat_o: signal is true;
attribute useioff of crc_o: signal is true;
attribute syn_useioff: boolean;
attribute syn_useioff of dat_i: signal is true;
attribute syn_useioff of pad_dat_i: signal is true;
attribute syn_useioff of dat_o: signal is true;
attribute syn_useioff of crc_o: signal is true;
end ccsds_rxtx_crc;
--=============================================================================
......
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_oversampler
---- Version: 1.0.0
---- Description:
---- Insert OSR-1 '0' between symbols
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary rxtx oversampler inputs and outputs
--=============================================================================
entity ccsds_rxtx_oversampler is
generic(
constant CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer := 4;
constant CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: std_logic := '0';
constant CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
-- outputs
sam_o: out std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end ccsds_rxtx_oversampler;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_rxtx_oversampler is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKOVERSAMPLERP0 : if (CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO mod 2 /= 0) generate
process
begin
report "ERROR: OVERSAMPLING RATIO HAS TO BE A MULTIPLE OF 2" severity failure;
wait;
end process;
end generate CHKOVERSAMPLERP0;
CHKOVERSAMPLERP1 : if (CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO = 0) generate
process
begin
report "ERROR: OVERSAMPLING RATIO CANNOT BE 0" severity failure;
wait;
end process;
end generate CHKOVERSAMPLERP1;
-- internal processing
--=============================================================================
-- Begin of osrp
-- Insert all 0 samples
--=============================================================================
-- read: rst_i, sam_i
-- write: sam_o
-- r/w:
OSRP: process (clk_i)
variable samples_counter: integer range 0 to CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1 := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
sam_o <= (others => '0');
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
else
if (sam_val_i = '1') then
sam_val_o <= '1';
if (CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING = '1') then
if (samples_counter <= 0) then
sam_o <= (others => '0');
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
else
if (samples_counter = CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO/2) then
sam_o <= sam_i;
else
sam_o <= (others => '0');
end if;
samples_counter := samples_counter - 1;
end if;
else
if (samples_counter <= 0) then
sam_o <= sam_i;
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
else
sam_o <= (others => '0');
samples_counter := samples_counter - 1;
end if;
end if;
else
sam_val_o <= '0';
end if;
end if;
end if;
end process;
end structure;
......@@ -39,6 +39,4 @@ package ccsds_rxtx_parameters is
-- PHYSICAL LAYER
constant TX_PHYS_SIG_QUANT_DEPTH: integer := 16;-- DIGITAL PROCESSING QUANTIFICATION DEPTH IN BITS NUMBER
constant RX_PHYS_SIG_QUANT_DEPTH: integer := 16;-- DIGITAL PROCESSING QUANTIFICATION DEPTH IN BITS NUMBER
--constant TX_PHYSICAL_SIGNAL_MODULATION_MAPPING : integer := 2; -- I&Q MODULATION MAPPING (2^PHYSICAL_MODULATION-PSK)
--constant TX_PHYSICAL_SIGNAL_OSR : integer := 8; -- OSR VALUE
end ccsds_rxtx_parameters;
This diff is collapsed.
This diff is collapsed.
......@@ -3,7 +3,7 @@
---- Design Name: ccsds_tx
---- Version: 1.0.0
---- Description:
---- TO BE DONE
---- CCSDS compliant TX
-------------------------------
---- Author(s):
---- Guillaume Rembert
......@@ -25,12 +25,15 @@ use ieee.std_logic_1164.all;
--=============================================================================
entity ccsds_tx is
generic (
CCSDS_TX_DATA_BUS_SIZE: integer;
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
constant CCSDS_TX_BITS_PER_SYMBOL: integer := 1;
constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=PSK / 2=GMSK
constant CCSDS_TX_DATA_BUS_SIZE: integer;
constant CCSDS_TX_OVERSAMPLING_RATIO: integer := 4;
constant CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
);
port(
-- inputs
clk_i: in std_logic; -- transmitted data clock
clk_i: in std_logic; -- transmitted samples clock
dat_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0); -- transmitted parallel data input
dat_ser_i: in std_logic; -- transmitted serial data input
dat_val_i: in std_logic; -- transmitted data valid input
......@@ -38,9 +41,6 @@ entity ccsds_tx is
in_sel_i: in std_logic; -- parallel / serial input selection
rst_i: in std_logic; -- system reset input
-- outputs
buf_bit_ful_o: out std_logic; -- bits buffer status indicator
buf_dat_ful_o: out std_logic; -- data buffer status indicator
buf_fra_ful_o: out std_logic; -- frames buffer status indicator
clk_o: out std_logic; -- output samples clock
ena_o: out std_logic; -- enabled status indicator
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
......@@ -54,11 +54,17 @@ end ccsds_tx;
architecture structure of ccsds_tx is
component ccsds_tx_manager is
generic(
CCSDS_TX_MANAGER_DATA_BUS_SIZE : integer
CCSDS_TX_MANAGER_BITS_PER_SYMBOL: integer;
CCSDS_TX_MANAGER_MODULATION_TYPE: integer;
CCSDS_TX_MANAGER_DATA_BUS_SIZE : integer;
CCSDS_TX_MANAGER_OVERSAMPLING_RATIO: integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
clk_bit_o: out std_logic;
clk_dat_o: out std_logic;
clk_sam_o: out std_logic;
clk_sym_o: out std_logic;
rst_i: in std_logic;
ena_i: in std_logic;
ena_o: out std_logic;
......@@ -75,30 +81,31 @@ architecture structure of ccsds_tx is
CCSDS_TX_DATALINK_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
clk_bit_i: in std_logic;
clk_dat_i: in std_logic;
rst_i: in std_logic;
dat_val_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
buf_dat_ful_o: out std_logic;
buf_fra_ful_o: out std_logic;
buf_bit_ful_o: out std_logic
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0)
);
end component;
component ccsds_tx_physical_layer is
generic(
CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH : integer;
CCSDS_TX_PHYSICAL_DATA_BUS_SIZE : integer
CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL: integer;
CCSDS_TX_PHYSICAL_MODULATION_TYPE: integer;
CCSDS_TX_PHYSICAL_DATA_BUS_SIZE: integer;
CCSDS_TX_PHYSICAL_OVERSAMPLING_RATIO: integer;
CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
clk_sam_i: in std_logic;
clk_sym_i: in std_logic;
rst_i: in std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
dat_val_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_PHYSICAL_DATA_BUS_SIZE-1 downto 0)
dat_i: in std_logic_vector(CCSDS_TX_PHYSICAL_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic
);
end component;
......@@ -106,17 +113,26 @@ architecture structure of ccsds_tx is
signal wire_data_valid_d: std_logic;
signal wire_data_m: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_data_d: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_clk_m: std_logic;
signal wire_clk_dat: std_logic;
signal wire_clk_sam: std_logic;
signal wire_clk_sym: std_logic;
signal wire_clk_bit: std_logic;
signal wire_rst_m: std_logic;
begin
tx_manager_1: ccsds_tx_manager
tx_manager_0: ccsds_tx_manager
generic map(
CCSDS_TX_MANAGER_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE
CCSDS_TX_MANAGER_BITS_PER_SYMBOL => CCSDS_TX_BITS_PER_SYMBOL,
CCSDS_TX_MANAGER_MODULATION_TYPE => CCSDS_TX_MODULATION_TYPE,
CCSDS_TX_MANAGER_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_TX_MANAGER_OVERSAMPLING_RATIO => CCSDS_TX_OVERSAMPLING_RATIO
)
port map(
clk_i => clk_i,
clk_o => wire_clk_m,
clk_bit_o => wire_clk_bit,
clk_dat_o => wire_clk_dat,
clk_sam_o => wire_clk_sam,
clk_sym_o => wire_clk_sym,
rst_i => rst_i,
ena_i => ena_i,
ena_o => ena_o,
......@@ -127,34 +143,35 @@ begin
dat_val_o => wire_data_valid_m,
dat_o => wire_data_m
);
tx_datalink_layer_1: ccsds_tx_datalink_layer
tx_datalink_layer_0: ccsds_tx_datalink_layer
generic map(
CCSDS_TX_DATALINK_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE
)
port map(
clk_i => wire_clk_m,
clk_dat_i => wire_clk_dat,
clk_bit_i => wire_clk_bit,
rst_i => rst_i,
dat_val_i => wire_data_valid_m,
dat_i => wire_data_m,
dat_val_o => wire_data_valid_d,
dat_o => wire_data_d,
buf_dat_ful_o => buf_dat_ful_o,
buf_fra_ful_o => buf_fra_ful_o,
buf_bit_ful_o => buf_bit_ful_o
dat_o => wire_data_d
);
tx_physical_layer_1: ccsds_tx_physical_layer
tx_physical_layer_0: ccsds_tx_physical_layer
generic map(
CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH => CCSDS_TX_PHYS_SIG_QUANT_DEPTH,
CCSDS_TX_PHYSICAL_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE
CCSDS_TX_PHYSICAL_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_TX_PHYSICAL_MODULATION_TYPE => CCSDS_TX_MODULATION_TYPE,
CCSDS_TX_PHYSICAL_BITS_PER_SYMBOL => CCSDS_TX_BITS_PER_SYMBOL,
CCSDS_TX_PHYSICAL_OVERSAMPLING_RATIO => CCSDS_TX_OVERSAMPLING_RATIO
)
port map(
clk_i => wire_clk_m,
clk_o => clk_o,
clk_sym_i => wire_clk_sym,
clk_sam_i => wire_clk_sam,
rst_i => rst_i,
sam_i_o => sam_i_o,
sam_q_o => sam_q_o,
dat_val_i => wire_data_valid_d,
dat_i => wire_data_d
dat_i => wire_data_d,
dat_val_i => wire_data_valid_d
);
clk_o <= wire_clk_sam;
end structure;
......@@ -28,20 +28,18 @@ entity ccsds_tx_datalink_layer is
generic (
constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer := 32; -- in bits
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 24; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
);
port(
-- inputs
clk_i: in std_logic;
clk_bit_i: in std_logic;
clk_dat_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
buf_bit_ful_o: out std_logic;
buf_dat_ful_o: out std_logic;
buf_fra_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
......@@ -83,11 +81,13 @@ architecture structure of ccsds_tx_datalink_layer is
end component;
-- internal constants
constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8;
constant FRAME_OUTPUT_WORDS: integer := FRAME_OUTPUT_SIZE/CCSDS_TX_DATALINK_DATA_BUS_SIZE;
-- interconnection signals
signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
signal wire_framer_data_valid: std_logic;
signal wire_coder_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8-1 downto 0);
signal wire_coder_data: std_logic_vector(FRAME_OUTPUT_SIZE-1 downto 0);
signal wire_coder_data_valid: std_logic;
-- components instanciation and mapping
......@@ -101,7 +101,7 @@ architecture structure of ccsds_tx_datalink_layer is
CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_TX_DATALINK_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
clk_i => clk_dat_i,
rst_i => rst_i,
dat_val_i => dat_val_i,
dat_i => dat_i,
......@@ -114,17 +114,51 @@ architecture structure of ccsds_tx_datalink_layer is
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8
)
port map(
clk_i => clk_i,
clk_i => clk_dat_i,
dat_i => wire_framer_data,
dat_val_i => wire_framer_data_valid,
rst_i => rst_i,
dat_val_o => wire_coder_data_valid,
dat_o => wire_coder_data
);
buf_dat_ful_o <= '0';
dat_val_o <= wire_coder_data_valid;
dat_o <= wire_coder_data(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
-- internal processing
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
--=============================================================================
-- read: rst_i, wire_coder_data, wire_coder_data_valid
-- write: dat_o, dat_val_o
-- r/w:
BITSOUTPUTP: process (clk_bit_i)
variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
variable current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_bit_i) then
-- reset signal received
if (rst_i = '1') then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
dat_o <= (others => '0');
dat_val_o <= '0';
else
-- generating valid bits output words
if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
next_word_pointer := FRAME_OUTPUT_WORDS - 2;
dat_val_o <= '1';
else
dat_val_o <= '1';
dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
if (next_word_pointer = 0) then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
else
next_word_pointer := next_word_pointer - 1;
end if;
end if;
end if;
end if;
end process;
end structure;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_filter
---- Version: 1.0.0
---- Description:
---- Transform symbols to samples, oversample signal and filter it with SRRC filter
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx filter inputs and outputs
--=============================================================================
entity ccsds_tx_filter is
generic(
constant CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer; -- in bits
constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_FILTER_OFFSET_PSK: std_logic := '1';
constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
sym_i_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_q_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
-- outputs
sam_i_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end ccsds_tx_filter;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_filter is
component ccsds_rxtx_oversampler is
generic(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: std_logic;
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
rst_i: in std_logic;
sam_o: out std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
component ccsds_rxtx_srrc is
generic(
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
sam_o: out std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal wire_sam_i: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_q: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_i_val: std_logic := '0';
signal wire_sam_q_val: std_logic := '0';
signal wire_sam_i_osr: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_q_osr: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
signal wire_sam_i_osr_val: std_logic;
signal wire_sam_q_osr_val: std_logic;
signal wire_sam_i_srrc_val: std_logic;
signal wire_sam_q_srrc_val: std_logic;
-- components instanciation and mapping
begin
tx_oversampler_i_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => '0',
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_i,
sam_val_i => wire_sam_i_val,
rst_i => rst_i,
sam_val_o => wire_sam_i_osr_val,
sam_o => wire_sam_i_osr
);
tx_srrc_i_0: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_i_osr,
sam_val_i => wire_sam_i_osr_val,
rst_i => rst_i,
sam_o => sam_i_o,
sam_val_o => wire_sam_i_srrc_val
);
-- BPSK
BPSK_GENERATION: if (CCSDS_TX_FILTER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_FILTER_MODULATION_TYPE = 2) generate
sam_q_o <= (others => '0');
wire_sam_q_srrc_val <= '1';
end generate BPSK_GENERATION;
-- nPSK
NPSK_GENERATION: if (CCSDS_TX_FILTER_MODULATION_TYPE /= 2) or (CCSDS_TX_FILTER_BITS_PER_SYMBOL /= 1) generate
tx_oversampler_q_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_PSK,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_q,
sam_val_i => wire_sam_q_val,
rst_i => rst_i,
sam_val_o => wire_sam_q_osr_val,
sam_o => wire_sam_q_osr
);
tx_srrc_q_0: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
clk_i => clk_i,
sam_i => wire_sam_q_osr,
sam_val_i => wire_sam_q_osr_val,
rst_i => rst_i,
sam_o => sam_q_o,
sam_val_o => wire_sam_q_srrc_val
);
end generate NPSK_GENERATION;
--Valid samples indicator
sam_val_o <= wire_sam_i_srrc_val and wire_sam_q_srrc_val;
-- presynthesis checks
CHKFILTERP0: if (CCSDS_TX_FILTER_BITS_PER_SYMBOL > 2*(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1)) generate
process
begin
report "ERROR: BITS PER SYMBOL CANNOT BE HIGHER THAN 2*(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1)" severity failure;
wait;
end process;