Commit 48e03628 authored by Guillaume REMBERT's avatar Guillaume REMBERT

Differential coder as dedicated block + deplacement to datalink layer for...

Differential coder as dedicated block + deplacement to datalink layer for pre-convolutionnal coder differential encoding capability
parent e1ae5264
-------------------------------
Project: EurySPACE
Version: 1.0.0
Date: 2016/13/03
-------------------------------
Author(s):
Guillaume REMBERT
......
......@@ -21,6 +21,7 @@ files =
ccsds_rx_physical_layer.vhd
ccsds_tx.vhd
ccsds_tx_coder.vhd
ccsds_tx_coder_differential.vhd
ccsds_tx_datalink_layer.vhd
ccsds_tx_filter.vhd
ccsds_tx_footer.vhd
......
This diff is collapsed.
......@@ -130,6 +130,7 @@ architecture structure of ccsds_rxtx_top is
dat_ser_i: in std_logic;
buf_ful_o: out std_logic;
clk_o: out std_logic;
idl_o: out std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
ena_o: out std_logic
......@@ -190,6 +191,7 @@ begin
dat_ser_i => tx_dat_ser_i,
buf_ful_o => wire_tx_buf_ful,
clk_o => tx_clk_o,
idl_o => tx_idl_o,
sam_i_o => tx_sam_i_o,
sam_q_o => tx_sam_q_o,
ena_o => tx_ena_o
......
......@@ -27,7 +27,7 @@ entity ccsds_tx is
generic (
constant CCSDS_TX_BITS_PER_SYMBOL: integer := 1;
constant CCSDS_TX_BUFFER_SIZE: integer := 16; -- max number of words stored for burst write at full speed when datalinklayer is full
constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=QAM/QPSK / 2=GMSK
constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=QAM/QPSK / 2=BPSK
constant CCSDS_TX_DATA_BUS_SIZE: integer;
constant CCSDS_TX_OVERSAMPLING_RATIO: integer := 4; -- symbols to samples over-sampling ratio
constant CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
......@@ -98,7 +98,8 @@ architecture structure of ccsds_tx is
end component;
component ccsds_tx_datalink_layer is
generic(
CCSDS_TX_DATALINK_DATA_BUS_SIZE : integer
CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer;
CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer
);
port(
clk_bit_i: in std_logic;
......@@ -186,7 +187,8 @@ begin
);
tx_datalink_layer_0: ccsds_tx_datalink_layer
generic map(
CCSDS_TX_DATALINK_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE
CCSDS_TX_DATALINK_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_BITS_PER_SYMBOL
)
port map(
clk_dat_i => wire_clk_dat,
......
......@@ -25,7 +25,9 @@ use ieee.std_logic_1164.all;
entity ccsds_tx_coder is
generic(
constant CCSDS_TX_CODER_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer -- in bits
constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword (should be equal to bits per symbol of lower link)
constant CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean -- Enable differential coder
);
port(
-- inputs
......@@ -43,6 +45,20 @@ end ccsds_tx_coder;
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_coder is
component ccsds_tx_coder_differential is
generic(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_randomizer is
generic(
CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer
......@@ -58,24 +74,26 @@ architecture structure of ccsds_tx_coder is
end component;
component ccsds_tx_synchronizer is
generic(
CCSDS_TX_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
CCSDS_TX_ASM_DATA_BUS_SIZE: integer -- in bits
CCSDS_TX_ASM_LENGTH: integer;
CCSDS_TX_ASM_DATA_BUS_SIZE: integer
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal wire_coder_diff_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
signal wire_coder_diff_dat_val_o: std_logic;
signal wire_randomizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
signal wire_randomizer_dat_val_o: std_logic;
signal wire_synchronizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
signal wire_synchronizer_dat_val_o: std_logic;
-- components instanciation and mapping
begin
tx_coder_randomizer_0: ccsds_tx_randomizer
......@@ -90,19 +108,49 @@ architecture structure of ccsds_tx_coder is
dat_val_o => wire_randomizer_dat_val_o,
dat_o => wire_randomizer_dat_o
);
tx_coder_synchronizer_0: ccsds_tx_synchronizer
generic map(
CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
);
NODIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = false) generate
tx_coder_synchronizer_0: ccsds_tx_synchronizer
generic map(
CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
);
end generate NODIFFCODERGENP;
DIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = true) generate
tx_coder_synchronizer_0: ccsds_tx_synchronizer
generic map(
CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => wire_synchronizer_dat_val_o,
dat_o => wire_synchronizer_dat_o
);
tx_coder_differential_0: ccsds_tx_coder_differential
generic map(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_synchronizer_dat_val_o,
dat_i => wire_synchronizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
);
end generate DIFFCODERGENP;
-- presynthesis checks
-- internal processing
end structure;
......@@ -19,7 +19,6 @@
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx datalink layer inputs and outputs
......@@ -27,7 +26,9 @@ use ieee.math_real.all;
entity ccsds_tx_datalink_layer is
generic (
constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer := 32; -- in bits
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
......@@ -71,6 +72,8 @@ architecture structure of ccsds_tx_datalink_layer is
end component;
component ccsds_tx_coder is
generic(
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
CCSDS_TX_CODER_ASM_LENGTH: integer
);
......@@ -117,7 +120,9 @@ architecture structure of ccsds_tx_datalink_layer is
tx_datalink_coder_0: ccsds_tx_coder
generic map(
CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
)
port map(
clk_i => clk_dat_i,
......@@ -127,15 +132,35 @@ architecture structure of ccsds_tx_datalink_layer is
dat_val_o => wire_coder_data_valid,
dat_o => wire_coder_data
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
--=============================================================================
-- read: rst_i, wire_coder_data, wire_coder_data_valid
-- write: dat_o, dat_val_o
-- read: rst_i, wire_coder_data_valid
-- write: dat_val_o
-- r/w:
BITSVALIDP: process (clk_dat_i)
begin
-- on each clock rising edge
if rising_edge(clk_dat_i) then
-- reset signal received
if (rst_i = '1') then
dat_val_o <= '0';
else
if (wire_coder_data_valid = '1') then
dat_val_o <= '1';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
--=============================================================================
-- read: rst_i, wire_coder_data
-- write: dat_o
-- r/w:
BITSOUTPUTP: process (clk_bit_i)
variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
......@@ -147,16 +172,13 @@ architecture structure of ccsds_tx_datalink_layer is
if (rst_i = '1') then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
dat_o <= (others => '0');
dat_val_o <= '0';
else
-- generating valid bits output words
if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
next_word_pointer := FRAME_OUTPUT_WORDS - 2;
dat_val_o <= '1';
else
dat_val_o <= '1';
dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
if (next_word_pointer = 0) then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
......
......@@ -26,7 +26,7 @@ entity ccsds_tx_filter is
generic(
constant CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer; -- in bits
constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_FILTER_OFFSET_PSK: boolean := true;
constant CCSDS_TX_FILTER_OFFSET_IQ: boolean := true;
constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer
);
......@@ -128,7 +128,7 @@ architecture structure of ccsds_tx_filter is
tx_oversampler_q_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_PSK,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_IQ,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
......
......@@ -20,7 +20,6 @@
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx mapper inputs and outputs
......@@ -28,7 +27,6 @@ use ieee.numeric_std.all;
entity ccsds_tx_mapper is
generic(
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer := 1; -- For QAM - 1 bit/symbol <=> QPSK/4-QAM - 2 bits/symbol <=> 16-QAM - 3 bits/symbol <=> 64-QAM - ... - N bits/symbol <=> 2^(N*2)-QAM
constant CCSDS_TX_MAPPER_DIFFERENTIAL_CODER: boolean := false; -- Differential coder activation
constant CCSDS_TX_MAPPER_GRAY_CODER: std_logic := '1'; -- Gray coder activation
constant CCSDS_TX_MAPPER_MODULATION_TYPE: integer := 1; -- 1=QPSK/QAM - 2=BPSK
constant CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer -- in bits
......@@ -53,8 +51,6 @@ architecture structure of ccsds_tx_mapper is
-- internal constants
constant MAPPER_SYMBOL_NUMBER_PER_CHANNEL: integer := CCSDS_TX_MAPPER_DATA_BUS_SIZE*CCSDS_TX_MAPPER_MODULATION_TYPE/(2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-- internal variable signals
signal symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
signal prev_sym: std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0) := (others => '0');
-- components instanciation and mapping
begin
-- presynthesis checks
......@@ -88,6 +84,7 @@ architecture structure of ccsds_tx_mapper is
-- write: sym_i_o, sym_q_o
-- r/w:
MAPPERP: process (clk_i)
variable symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
......@@ -95,45 +92,24 @@ architecture structure of ccsds_tx_mapper is
if (rst_i = '1') then
sym_i_o <= (others => '0');
sym_q_o <= (others => '0');
prev_sym <= (others => '0');
symbol_counter <= MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
sym_val_o <= '0';
else
if (dat_val_i = '1') then
sym_val_o <= '1';
-- Differential coding
if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
-- BPSK
if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
prev_sym <= dat_i(symbol_counter-1 downto symbol_counter-1);
-- QPSK/QAM
else
prev_sym <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
end if;
-- BPSK mapping
if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
sym_q_o(0) <= '0';
if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
sym_i_o(0 downto 0) <= dat_i(symbol_counter-1 downto symbol_counter-1) xor prev_sym;
else
sym_i_o(0) <= dat_i(symbol_counter-1);
end if;
sym_i_o(0) <= dat_i(symbol_counter-1);
-- QPSK/QAM mapping
else
if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
--TODO HERE: GRAY MAPPING
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL) xor prev_sym;
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL) xor dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
else
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
if (symbol_counter = 1) then
symbol_counter <= MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
symbol_counter := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
else
symbol_counter <= symbol_counter - 1;
symbol_counter := symbol_counter - 1;
end if;
else
sym_val_o <= '0';
......
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