Commit 5d65708a authored by Guillaume REMBERT's avatar Guillaume REMBERT

Major rework based on new architecture + added CRC component and TX manager

parent bc99fd64
......@@ -23,23 +23,23 @@ use ieee.std_logic_1164.all;
entity ccsds_rx is
generic (
CCSDS_RX_PHYS_SIG_QUANT_DEPTH : integer := 16;
CCSDS_RX_DATA_OUTPUT_TYPE: integer := 0;
CCSDS_RX_DATA_INPUT_TYPE: integer := 0;
CCSDS_RX_DATA_BUS_SIZE: integer := 32
);
port(
rst_i: in std_logic; -- system reset input
ena_i: in std_logic; -- system enable input
clk_i: in std_logic; -- input samples clock
i_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
q_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
if_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- intermediate frequency real parallel samples
i_samples_ser_i: in std_logic; -- in-phased serial complex samples
q_samples_ser_i: in std_logic; -- quadrature-phased serial complex samples
if_samples_ser_i: in std_logic; -- intermediate-frequency serial real samples
clk_o: out std_logic; -- received data clock
data_par_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
data_ser_o: out std_logic -- received data serial output
i_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
q_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
data_next_i: in std_logic; -- next data
data_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
irq_o: out std_logic; -- data ready to be read / IRQ signal
data_valid_o: out std_logic; -- data valid
-- Monitoring outputs
data_buffer_full_o: out std_logic; -- data buffer status indicator
frames_buffer_full_o: out std_logic; -- frames buffer status indicator
bits_buffer_full_o: out std_logic; -- bits buffer status indicator
enabled_o: out std_logic -- enabled status indicator
);
end ccsds_rx;
......@@ -50,12 +50,12 @@ architecture structure of ccsds_rx is
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
data_i: in std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_buffer_full_o: out std_logic;
frames_buffer_full_o: out std_logic;
bits_buffer_full_o: out std_logic
);
end component;
component ccsds_rx_physical_layer is
......@@ -67,19 +67,13 @@ architecture structure of ccsds_rx is
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
i_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
q_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
if_samples_par_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
i_samples_ser_i: in std_logic;
q_samples_ser_i: in std_logic;
if_samples_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
i_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
q_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0)
);
end component;
signal wire_data_par: std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
signal wire_data_ser: std_logic;
signal wire_data_m: std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
signal wire_clk_m: std_logic;
signal wire_clk_i: std_logic;
......@@ -90,12 +84,12 @@ begin
)
port map(
clk_i => wire_clk_m,
clk_o => clk_o,
rst_i => rst_i,
data_par_i => wire_data_par,
data_ser_i => wire_data_ser,
data_par_o => data_par_o,
data_ser_o => data_ser_o
data_i => wire_data_m,
data_o => data_o,
data_buffer_full_o => data_buffer_full_o,
frames_buffer_full_o => frames_buffer_full_o,
bits_buffer_full_o => bits_buffer_full_o
);
rx_physical_layer_1: ccsds_rx_physical_layer
generic map(
......@@ -106,15 +100,11 @@ begin
clk_i => wire_clk_i,
clk_o => wire_clk_m,
rst_i => rst_i,
i_samples_par_i => i_samples_par_i,
q_samples_par_i => q_samples_par_i,
if_samples_par_i => if_samples_par_i,
i_samples_ser_i => i_samples_ser_i,
q_samples_ser_i => q_samples_ser_i,
if_samples_ser_i => if_samples_ser_i,
data_par_o => wire_data_par,
data_ser_o => wire_data_ser
i_samples_i => i_samples_i,
q_samples_i => q_samples_i,
data_o => wire_data_m
);
--=============================================================================
-- Begin of enablep
-- Enable/disable clk forwarding
......@@ -126,8 +116,10 @@ begin
begin
if (ena_i = '1') then
wire_clk_i <= clk_i;
enabled_o <= '1';
else
wire_clk_i <= '0';
enabled_o <= '0';
end if;
end process;
end structure;
......@@ -26,23 +26,26 @@ entity ccsds_rx_datalink_layer is
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
data_i: in std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_buffer_full_o: out std_logic;
frames_buffer_full_o: out std_logic;
bits_buffer_full_o: out std_logic
);
end ccsds_rx_datalink_layer;
-- internal processing
architecture rtl of ccsds_rx_datalink_layer is
begin
-- TEMPORARY NO CHANGE / DUMMY LINKLAYER
DATALINKP : process (clk_i, data_par_i, data_ser_i)
begin
data_o <= data_i;
data_buffer_full_o <= '0';
frames_buffer_full_o <= '0';
bits_buffer_full_o <= '0';
DATALINKP : process (clk_i, data_i)
begin
data_par_o <= data_par_i;
data_ser_o <= data_ser_i;
clk_o <= clk_i;
end process;
end rtl;
......@@ -31,14 +31,9 @@ entity ccsds_rx_physical_layer is
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
i_samples_par_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
q_samples_par_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
if_samples_par_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
i_samples_ser_i: in std_logic;
q_samples_ser_i: in std_logic;
if_samples_ser_i: in std_logic;
data_par_o: out std_logic_vector(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic
i_samples_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
q_samples_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto 0)
);
end ccsds_rx_physical_layer;
......@@ -50,6 +45,9 @@ architecture rtl of ccsds_rx_physical_layer is
-- architecture begin
--=============================================================================
begin
data_o(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH) <= q_samples_i;
data_o(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0) <= i_samples_i;
clk_o <= clk_i;
--=============================================================================
-- Begin of physicalp
-- TEST PURPOSES / DUMMY PHYSICAL LAYER PROCESS
......@@ -57,12 +55,8 @@ architecture rtl of ccsds_rx_physical_layer is
-- read: clk_i
-- write:
-- r/w:
PHYSICALP : process (clk_i, i_samples_par_i, q_samples_par_i, if_samples_par_i, i_samples_ser_i, q_samples_ser_i, if_samples_ser_i)
PHYSICALP : process (clk_i, i_samples_i, q_samples_i)
begin
data_par_o(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH) <= q_samples_par_i;
data_par_o(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0) <= i_samples_par_i;
data_ser_o <= i_samples_ser_i;
clk_o <= clk_i;
end process;
end rtl;
--=============================================================================
......
......@@ -9,17 +9,18 @@ src_files =
ccsds_rxtx_constants.vhd
ccsds_rxtx_functions.vhd
ccsds_rxtx_parameters.vhd
# ccsds_rxtx_serdes.vhd
ccsds_rxtx_buffer.vhd
ccsds_rxtx_crc.vhd
ccsds_rx.vhd
ccsds_rx_datalink_layer.vhd
ccsds_rx_physical_layer.vhd
ccsds_tx.vhd
ccsds_tx_manager.vhd
ccsds_tx_datalink_layer.vhd
ccsds_tx_physical_layer.vhd
ccsds_tx_framer.vhd
ccsds_tx_header.vhd
ccsds_tx_trailer.vhd
ccsds_tx_footer.vhd
# ccsds_rxtx_layer_1.vhdl
# ccsds_rxtx_layer_2.vhdl
# ccsds_rxtx_codec_ecc_crc.vhdl
......
This diff is collapsed.
......@@ -3,7 +3,7 @@
---- Design Name: ccsds_rxtx_buffer
---- Version: 1.0.0
---- Description:
---- Simple FIFO circular buffer
---- FIFO circular buffer
-------------------------------
---- Author(s):
---- Guillaume REMBERT
......@@ -13,24 +13,27 @@
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
---- 2016/10/20: major corrections and optimizations
-------------------------------
--FIXME: 1 WORD not used for storage
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary rxtx buffer
--=============================================================================
-- Entity declaration for ccsds_tx / unitary rxtx buffer inputs and outputs
--=============================================================================
entity ccsds_rxtx_buffer is
generic(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer := 32;
CCSDS_RXTX_BUFFER_SIZE : integer range 2 to 100000 := 256
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer;
CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
buf_empty_o: out std_logic;
buf_full_o: out std_logic;
buffer_empty_o: out std_logic;
buffer_full_o: out std_logic;
next_data_i: in std_logic;
data_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
data_valid_i: in std_logic;
......@@ -39,107 +42,82 @@ entity ccsds_rxtx_buffer is
);
end ccsds_rxtx_buffer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture rtl of ccsds_rxtx_buffer is
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := CCSDS_RXTX_BUFFER_SIZE-1;
-- interconnection signals
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
signal buffer_full: std_logic := '0';
signal buffer_empty: std_logic := '1';
type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE-1 downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
signal buffer_data: buffer_array;
signal buffer_data: buffer_array := (others => (others => '0'));
-- components instanciation and mapping
begin
begin
-- internal processing
BUFFERSTATEP : process (clk_i)
-- variable previous_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
--variable previous_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
if (rst_i = '0') then
buffer_full <= '0';
buffer_empty <= '1';
else
if (buffer_write_pos = buffer_read_pos) then
buffer_full <= '1';
buffer_empty <= '0';
--=============================================================================
-- Begin of bufferpushp
-- Store valid input data in buffer
--=============================================================================
-- read: data_valid_i, rst_i
-- write: buffer_write_pos, buffer_data, wire_buffer_full
-- r/w:
BUFFERPUSH : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
buffer_write_pos <= 0;
buffer_full_o <= '0';
else
buffer_full <= '0';
end if;
if (buffer_full = '0') then
if (buffer_read_pos+1 = CCSDS_RXTX_BUFFER_SIZE) then
if (buffer_write_pos = 0) then
buffer_empty <= '1';
else
buffer_empty <= '0';
end if;
-- check if buffer is full
if ((buffer_write_pos+1) mod CCSDS_RXTX_BUFFER_SIZE = buffer_read_pos) then
buffer_full_o <= '1';
else
if (buffer_read_pos+1 = buffer_write_pos) then
buffer_empty <= '1';
else
buffer_empty <= '0';
buffer_full_o <= '0';
if (data_valid_i = '1') then
-- copy data to buffer mem
buffer_data(buffer_write_pos) <= data_i;
buffer_write_pos <= (buffer_write_pos + 1) mod CCSDS_RXTX_BUFFER_SIZE;
end if;
end if;
end if;
end if;
end if;
end process;
-- PUSH - WRITE OPERATIONS
BUFFERPUSH : process (clk_i)
variable push_state: std_logic := '0';
begin
if rising_edge(clk_i) then
if (rst_i = '0') then
push_state := '0';
buffer_write_pos <= 0;
else
-- check if buffer is full
if (buffer_full = '0') and (data_valid_i = '1') and (push_state = '0') then
-- copy data to buffer mem
buffer_data(buffer_write_pos) <= data_i;
push_state := '1';
--end of circular buffer is reached
if (buffer_write_pos+1 = CCSDS_RXTX_BUFFER_SIZE) then
buffer_write_pos <= 0;
else
buffer_write_pos <= buffer_write_pos + 1;
end if;
end process;
--=============================================================================
-- Begin of bufferpullp
-- Read data from buffer
--=============================================================================
-- read: wire_buffer_empty, next_data_i, rst_i
-- write: data_o, buffer_read_pos, data_valid_o, wire_buffer_empty
-- r/w:
BUFFERPULLP : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
buffer_read_pos <= 0;
data_valid_o <= '0';
data_o <= (others => '0');
buffer_empty_o <= '1';
else
push_state := '0';
end if;
end if;
end if;
end process;
-- PULL - READ OPERATIONS
BUFFERPULLP : process (clk_i)
variable pull_state: std_logic := '0';
begin
if rising_edge(clk_i) then
if (rst_i = '0') then
pull_state := '0';
buffer_read_pos <= CCSDS_RXTX_BUFFER_SIZE-1;
else
-- check if buffer is empty
if (buffer_empty = '0') and (next_data_i = '1') and (pull_state = '0') then
data_valid_o <= '1';
pull_state := '1';
if ((buffer_read_pos + 1) = CCSDS_RXTX_BUFFER_SIZE) then
buffer_read_pos <= 0;
-- check if buffer is empty
if (buffer_read_pos = buffer_write_pos) then
buffer_empty_o <= '1';
data_valid_o <= '0';
else
buffer_read_pos <= buffer_read_pos + 1;
buffer_empty_o <= '0';
if (next_data_i = '1') then
data_valid_o <= '1';
data_o <= buffer_data(buffer_read_pos);
buffer_read_pos <= (buffer_read_pos + 1) mod CCSDS_RXTX_BUFFER_SIZE;
else
data_valid_o <= '0';
end if;
end if;
else
pull_state := '0';
data_valid_o <= '0';
end if;
end if;
end if;
end process;
buf_empty_o <= buffer_empty;
buf_full_o <= buffer_full;
data_o <= buffer_data(buffer_read_pos);
clk_o <= clk_i;
end process;
end rtl;
......@@ -16,5 +16,5 @@
-------------------------------
package ccsds_rxtx_constants is
constant TX_OK: integer := 1; -- datalink ok
constant RXTX_CST: integer := 1; -- DUMMY USELESS CONSTANT
end ccsds_rxtx_constants;
This diff is collapsed.
......@@ -13,6 +13,7 @@
-------------------------------
---- Changes list:
---- 2015/12/28: initial release
---- 2016/10/20: added reverse_std_logic_vector function + rework sim_generate_random_std_logic_vector for > 32 bits vectors
-------------------------------
-- libraries used
......@@ -22,21 +23,40 @@ use ieee.numeric_std.all;
use ieee.math_real.all;
package ccsds_rxtx_functions is
-- simulation : testbench only functions
procedure simGetRandomBitVector(vectorSize : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
-- synthetizable functions
-- synthesable functions
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector;
-- simulation / testbench only functions
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
end ccsds_rxtx_functions;
package body ccsds_rxtx_functions is
procedure simGetRandomBitVector(vectorSize : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector) is
variable rand : real := 0.0;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(input'RANGE);
alias output: std_logic_vector(input'REVERSE_RANGE) is input;
begin
for i in output'RANGE loop
result(i) := output(i);
end loop;
return result;
end;
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector) is
variable rand: real := 0.0;
variable temp: std_logic_vector(31 downto 0);
begin
-- report "DEBUG: Seeds values => seed1 = " & positive'image(seed1) & " seed2 = " & positive'image(seed2) severity warning;
uniform(seed1, seed2, rand);
-- report "DEBUG: Random value => rand = " & real'image(rand) severity warning;
-- report "DEBUG: Seeds values => seed1 = " & positive'image(seed1) & " seed2 = " & positive'image(seed2) severity warning;
rand := rand*(2**(real(vectorSize)-1.0));
-- report "DEBUG: Random value => rand = " & real'image(rand) severity warning;
result := std_logic_vector(to_unsigned(integer(rand),vectorSize));
end simGetRandomBitVector;
if (vector_size <= 32) then
uniform(seed1, seed2, rand);
rand := rand*(2**(real(vector_size)-1.0));
result := std_logic_vector(to_unsigned(integer(rand),vector_size));
else
uniform(seed1, seed2, rand);
for i in 0 to vector_size-1 loop
uniform(seed1, seed2, rand);
rand := rand*(2**(real(32)-1.0));
temp := std_logic_vector(to_unsigned(integer(rand),32));
result(i) := temp(i mod 32);
end loop;
end if;
end sim_generate_random_std_logic_vector;
end ccsds_rxtx_functions;
......@@ -13,6 +13,7 @@
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/20: rework / remove non-systems parameters / each component has his own parameters set at proper level
-------------------------------
-- libraries used
......@@ -21,23 +22,14 @@ use ieee.std_logic_1164.all;
package ccsds_rxtx_parameters is
-- SYSTEM CONFIGURATION
constant RXTX_SYSTEM_WB_DATA_BUS_SIZE: integer := 32;-- Wishbone slave data bus size
constant RXTX_SYSTEM_WB_ADDR_BUS_SIZE: integer := 4;-- Wishbone slave address bus size
constant RXTX_SYSTEM_WB_DATA_BUS_SIZE: integer := 32;-- Wishbone slave data bus size (bits)
constant RXTX_SYSTEM_WB_ADDR_BUS_SIZE: integer := 4;-- Wishbone slave address bus size (bits)
-- RX CONFIGURATION
constant RX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of RX at startup
constant RX_SYSTEM_AUTO_EXTERNAL: std_logic := '0';--Automatic configuration of RX to use external clock and data
constant RX_SYSTEM_DATA_BUS_SIZE: integer := 32;-- RX parallel input data bus size
constant RX_SYSTEM_DATA_INPUT_TYPE: integer := 0;-- RX ext samples input type (0=serial i&q, 1=serial if, 2=parallel i&Q, 3=parallel if)
constant RX_SYSTEM_DATA_OUTPUT_TYPE: integer := 0;-- RX ext data output type (0=serial, 1=parallel)
constant RX_SYSTEM_DATA_DEFAULT_DATA: std_logic_vector(31 downto 0) := "01000000000000000000000000000010";
-- TX CONFIGURATION
constant TX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of TX at startup
constant TX_SYSTEM_AUTO_EXTERNAL: std_logic := '0';--Automatic configuration of RX to use external clock and data
constant TX_SYSTEM_DATA_BUS_SIZE: integer := 32;-- TX parallel input data bus size (bits)
constant TX_SYSTEM_DATA_BUFFER_SIZE: integer := 256;--TX parallel input data words buffer size (words of TX_SYSTEM_DATA_BUS_SIZE bits)
constant TX_SYSTEM_DATA_INPUT_TYPE: integer := 0;-- TX ext input data type (0=serial, 1=parallel)
constant TX_SYSTEM_DATA_OUTPUT_TYPE: integer := 0;-- TX ext output samples type (0= serial i&q, 1=serial if, 2=parallel i&Q, 3=parallel if)
constant TX_SYSTEM_DATA_DEFAULT_DATA: std_logic_vector(31 downto 0) := (others => '1');
constant TX_SYSTEM_DATA_BUFFER_SIZE: integer := 64;--TX parallel input data words buffer size (words of RXTX_SYSTEM_WB_DATA_BUS_SIZE bits)
-- LAYERS CONFIGURATION
-- APPLICATION LAYER
-- PRESENTATION LAYER
......@@ -45,9 +37,6 @@ package ccsds_rxtx_parameters is
-- TRANSPORT LAYER
-- NETWORK LAYER
-- DATALINK LAYER
constant TX_DATALINK_FRAME_LENGTH: integer := 32; -- datagram data size (Bytes)
constant TX_DATALINK_HEADER_LENGTH: integer := 5; -- datagram header length (Bytes)
constant TX_DATALINK_FOOTER_SIZE: integer := 2; -- datagram footer length (Bytes)
-- CCSDS HEADERS
constant TX_DATALINK_CCSDS_HEADERS_ENABLE: boolean := true;
constant TX_DATALINK_CCSDS_HEADERS_SPACECRAFT_ID: std_logic_vector(9 downto 0) := "1000000001"; -- INITIAL SPACECRAFT ID (SPECIFIC WORD / 10 BITS)
......
......@@ -4,7 +4,7 @@
---- Version: 1.0.0
---- Description:
---- This is the data serialiser/deserialiser
---- par -> ser require N cycles to finish
---- requires CCSDS_RXTX_SERDES_DEPTH clk cycles to finish
-------------------------------
---- Author(s):
---- Guillaume Rembert
......@@ -51,13 +51,13 @@ architecture rtl of ccsds_rxtx_serdes is
--=============================================================================
begin
--=============================================================================
-- Begin of serializerp
-- Begin of par2serp
-- Serialization of parrallel data received starting with MSB
--=============================================================================
-- read: clk_par_i, rst_i, data_par_i
-- write: data_ser_o
-- r/w:
SERIALIZERP : process (clk_par_i)
PAR2SERP : process (clk_par_i)
variable serdes_pnt: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
begin
-- on each clock rising edge
......@@ -81,13 +81,13 @@ architecture rtl of ccsds_rxtx_serdes is
end if;
end process;
--=============================================================================
-- Begin of deserializerp
-- Begin of ser2parp
-- Serialization of parrallel data received
--=============================================================================
-- read: clk_par_i, rst_i
-- write:
-- r/w:
-- DESERIALIZERP : process (clk_ser_i)
-- SER2PARP : process (clk_ser_i)
-- begin
-- data_o <= i_samples_i(0);
-- clk_o <= clk_i;
......
This diff is collapsed.
......@@ -13,57 +13,75 @@
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/19: rework
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
-- unitary tx external physical inputs and outputs
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx external physical inputs and outputs
--=============================================================================
entity ccsds_tx is
generic (
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer := 16;
CCSDS_TX_DATA_OUTPUT_TYPE: integer := 0;
CCSDS_TX_DATA_INPUT_TYPE: integer := 0;
CCSDS_TX_DATA_BUFFER_SIZE: integer := 256;
CCSDS_TX_DATA_BUS_SIZE: integer := 32
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer;
CCSDS_TX_DATA_BUS_SIZE: integer
);
port(
rst_i: in std_logic; -- system reset input
ena_i: in std_logic; -- system enable input
clk_i: in std_logic; -- transmitted data clock
input_sel_i: in std_logic; -- parallel / serial input selection
data_valid_i: in std_logic; -- transmitted data valid input
data_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0); -- transmitted parallel data input
data_ser_i: in std_logic; -- transmitted serial data input
clk_o: out std_logic; -- output samples clock
samples_valid_o: out std_logic;
i_samples_par_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
q_samples_par_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
if_samples_par_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
i_samples_ser_o: out std_logic;
q_samples_ser_o: out std_logic;
if_samples_ser_o: out std_logic;
buf_full_o: out std_logic
i_samples_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
q_samples_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
data_buffer_full_o: out std_logic; -- data buffer status indicator
frames_buffer_full_o: out std_logic; -- frames buffer status indicator
bits_buffer_full_o: out std_logic; -- bits buffer status indicator
enabled_o: out std_logic -- enabled status indicator
);
end ccsds_tx;
--=============================================================================
-- architecture declaration / internal connections
--=============================================================================
architecture structure of ccsds_tx is
component ccsds_tx_datalink_layer is
component ccsds_tx_manager is
generic(
CCSDS_TX_DATALINK_DATA_BUS_SIZE : integer;
CCSDS_TX_DATALINK_BUFFER_SIZE : integer
CCSDS_TX_MANAGER_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
data_valid_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
ena_i: in std_logic;
enabled_o: out std_logic;
input_sel_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
data_ser_i: in std_logic;
data_valid_i: in std_logic;
data_valid_o: out std_logic;
data_par_o: out std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
data_ser_o: out std_logic;
buf_full_o: out std_logic
data_o: out std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0)
);
end component;
component ccsds_tx_datalink_layer is
generic(
CCSDS_TX_DATALINK_DATA_BUS_SIZE : integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
data_valid_i: in std_logic;
data_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_valid_o: out std_logic;
data_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_buffer_full_o: out std_logic;
frames_buffer_full_o: out std_logic;
bits_buffer_full_o: out std_logic
);
end component;
component ccsds_tx_physical_layer is
......@@ -75,42 +93,52 @@ architecture structure of ccsds_tx is
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
samples_valid_o: out std_logic;
i_samples_par_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
q_samples_par_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
if_samples_par_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
i_samples_ser_o: out std_logic;
q_samples_ser_o: out std_logic;
if_samples_ser_o: out std_logic;
i_samples_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
q_samples_o: out std_logic_vector(CCSDS_TX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);