Commit b13a8fc0 authored by Guillaume REMBERT's avatar Guillaume REMBERT

Coder block implementation + LFSR component (Galois and Fibonacci) + ASM

parent d7c784a2
......@@ -9,6 +9,7 @@ files =
ccsds_rxtx_constants.vhd
ccsds_rxtx_crc.vhd
ccsds_rxtx_functions.vhd
ccsds_rxtx_lfsr.vhd
ccsds_rxtx_parameters.vhd
ccsds_rxtx_serdes.vhd
ccsds_rxtx_top.vhd
......@@ -16,12 +17,15 @@ files =
ccsds_rx_datalink_layer.vhd
ccsds_rx_physical_layer.vhd
ccsds_tx.vhd
ccsds_tx_manager.vhd
ccsds_tx_coder.vhd
ccsds_tx_datalink_layer.vhd
ccsds_tx_physical_layer.vhd
ccsds_tx_footer.vhd
ccsds_tx_framer.vhd
ccsds_tx_header.vhd
ccsds_tx_footer.vhd
ccsds_tx_manager.vhd
ccsds_tx_physical_layer.vhd
ccsds_tx_randomizer.vhd
ccsds_tx_synchronizer.vhd
file_type = vhdlSource
usage = sim synth
......
......@@ -23,6 +23,7 @@
---- 2016/10/25: adding framer sub-component test ressources + CRC checks
---- 2016/10/27: adding serdes sub-component test ressources
---- 2016/10/30: framer tests improvements
---- 2016/11/04: adding lfsr sub-component test ressources
-------------------------------
--TODO: functions for sub-components interactions and checks (wb_read, wb_write, buffer_read, ...)
......@@ -64,6 +65,12 @@ entity ccsds_rxtx_bench is
CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH: integer := 2;
CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH: integer := 6;
CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO: integer := 2;
-- LFSR
CCSDS_RXTX_BENCH_LFSR0_RESULT: std_logic_vector := "1111111101001000000011101100000010011010";
CCSDS_RXTX_BENCH_LFSR0_MEMORY_SIZE: integer := 8;
CCSDS_RXTX_BENCH_LFSR0_MODE: std_logic := '0';
CCSDS_RXTX_BENCH_LFSR0_POLYNOMIAL: std_logic_vector := x"A9";
CCSDS_RXTX_BENCH_LFSR0_SEED: std_logic_vector := x"FF";
-- SERDES
CCSDS_RXTX_BENCH_SERDES0_DEPTH: integer := 32;
-- simulation/test parameters
......@@ -73,6 +80,7 @@ entity ccsds_rxtx_bench is
CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER: integer:= 25;
CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER: integer := 25;
CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD: time := 20 ns;
CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD: time := 10 ns;
......@@ -83,6 +91,7 @@ entity ccsds_rxtx_bench is
CCSDS_RXTX_BENCH_START_BUFFER_WAIT_DURATION: time := 1500 ns;
CCSDS_RXTX_BENCH_START_CRC_WAIT_DURATION: time := 1500 ns;
CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION: time := 1500 ns;
CCSDS_RXTX_BENCH_START_LFSR_WAIT_DURATION: time := 1500 ns;
CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION: time := 1000 ns;
CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION: time := 500 ns;
CCSDS_RXTX_BENCH_START_SERDES_WAIT_DURATION: time := 1500 ns;
......@@ -179,6 +188,21 @@ architecture behaviour of ccsds_rxtx_bench is
dat_val_o: out std_logic
);
end component;
component ccsds_rxtx_lfsr is
generic(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer;
CCSDS_RXTX_LFSR_MEMORY_SIZE: integer;
CCSDS_RXTX_LFSR_MODE: std_logic;
CCSDS_RXTX_LFSR_POLYNOMIAL: std_logic_vector;
CCSDS_RXTX_LFSR_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_rxtx_serdes is
generic (
constant CCSDS_RXTX_SERDES_DEPTH : integer
......@@ -248,6 +272,9 @@ architecture behaviour of ccsds_rxtx_bench is
signal bench_sti_framer0_rst: std_logic;
signal bench_sti_framer0_data_valid: std_logic;
signal bench_sti_framer0_data: std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
-- lfsr
signal bench_sti_lfsr0_clk: std_logic;
signal bench_sti_lfsr0_rst: std_logic;
-- serdes
signal bench_sti_serdes0_clk: std_logic;
signal bench_sti_serdes0_rst: std_logic;
......@@ -290,6 +317,9 @@ architecture behaviour of ccsds_rxtx_bench is
-- framer
signal bench_res_framer0_data_valid: std_logic;
signal bench_res_framer0_data: std_logic_vector((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH)*8-1 downto 0);
-- lfsr
signal bench_res_lfsr0_data_valid: std_logic;
signal bench_res_lfsr0_data: std_logic_vector(CCSDS_RXTX_BENCH_LFSR0_RESULT'length-1 downto 0);
-- serdes
signal bench_res_serdes0_busy: std_logic;
signal bench_res_serdes0_data_par: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
......@@ -432,6 +462,20 @@ architecture behaviour of ccsds_rxtx_bench is
dat_val_o => bench_res_framer0_data_valid,
dat_o => bench_res_framer0_data
);
lfsr_001: ccsds_rxtx_lfsr
generic map(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_LFSR0_RESULT'length,
CCSDS_RXTX_LFSR_MEMORY_SIZE => CCSDS_RXTX_BENCH_LFSR0_MEMORY_SIZE,
CCSDS_RXTX_LFSR_MODE => CCSDS_RXTX_BENCH_LFSR0_MODE,
CCSDS_RXTX_LFSR_POLYNOMIAL => CCSDS_RXTX_BENCH_LFSR0_POLYNOMIAL,
CCSDS_RXTX_LFSR_SEED => CCSDS_RXTX_BENCH_LFSR0_SEED
)
port map(
clk_i => bench_sti_lfsr0_clk,
rst_i => bench_sti_lfsr0_rst,
dat_val_o => bench_res_lfsr0_data_valid,
dat_o => bench_res_lfsr0_data
);
serdes_001: ccsds_rxtx_serdes
generic map(
CCSDS_RXTX_SERDES_DEPTH => CCSDS_RXTX_BENCH_SERDES0_DEPTH
......@@ -535,6 +579,20 @@ architecture behaviour of ccsds_rxtx_bench is
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_lfsr0_clkp
-- bench_sti_lfsr0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_lfsr0_clk
-- r/w:
BENCH_STI_LFSR0_CLKP : process
begin
bench_sti_lfsr0_clk <= '1';
wait for CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD/2;
bench_sti_lfsr0_clk <= '0';
wait for CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_serdes0_clkp
-- bench_sti_serdes0_clk generation
--=============================================================================
......@@ -1157,6 +1215,39 @@ architecture behaviour of ccsds_rxtx_bench is
wait;
end process;
--=============================================================================
-- Begin of lfsrp
-- generation of lfsr subsystem read-write unit-tests
--=============================================================================
-- read:
-- write:
-- r/w:
LFSRP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_LFSR_WAIT_DURATION);
-- initial state tests:
-- behaviour tests:
report "LFSRP: START LFSR TESTS" severity note;
wait for (CCSDS_RXTX_BENCH_LFSR0_RESULT'length)*CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD;
if (bench_res_lfsr0_data_valid = '1') then
report "LFSRP: OK - LFSR output is valid" severity note;
if (bench_res_lfsr0_data = CCSDS_RXTX_BENCH_LFSR0_RESULT) then
report "LFSRP: OK - LFSR output is equal to expected output" severity note;
else
report "LFSRP: KO - LFSR output is different from expected output" severity warning;
end if;
else
report "LFSRP: KO - LFSR output is not valid" severity warning;
end if;
-- final state tests:
report "LFSRP: END LFSR TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of serdesp
-- generation of serdes subsystem unit-tests
--=============================================================================
......@@ -1377,6 +1468,7 @@ architecture behaviour of ccsds_rxtx_bench is
bench_sti_crc0_rst <= '1';
bench_sti_buffer0_rst <= '1';
bench_sti_framer0_rst <= '1';
bench_sti_lfsr0_rst <= '1';
-- wait for some time
wait for CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION;
report "RESETP: END RESET SIGNAL TEST" severity note;
......@@ -1385,6 +1477,7 @@ architecture behaviour of ccsds_rxtx_bench is
bench_sti_crc0_rst <= '0';
bench_sti_buffer0_rst <= '0';
bench_sti_framer0_rst <= '0';
bench_sti_lfsr0_rst <= '0';
-- do nothing
wait;
end process;
......
......@@ -186,7 +186,7 @@ entity ccsds_rxtx_crc is
constant CCSDS_RXTX_CRC_INPUT_REFLECTED: boolean := false; -- Reflect input on overall data (not currently used by standards) / WARNING - take over input bytes reflected parameter if activated
constant CCSDS_RXTX_CRC_LENGTH: integer := 2; -- CRC value depth - in Bytes
constant CCSDS_RXTX_CRC_OUTPUT_REFLECTED: boolean := false; -- Reflect output
constant CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector := x"1021"; -- Truncated polynomial / LSB <=> lower polynome (needs to be '1')
constant CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector := x"1021"; -- Truncated polynomial / MSB <=> lower polynome (needs to be '1')
constant CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED: boolean := false; -- Reflect polynomial
constant CCSDS_RXTX_CRC_SEED: std_logic_vector := x"FFFF" -- Initial value from register
);
......@@ -232,14 +232,14 @@ architecture rtl of ccsds_rxtx_crc is
CHKCRCP1 : if CCSDS_RXTX_CRC_POLYNOMIAL'length /= CCSDS_RXTX_CRC_LENGTH*8 generate
process
begin
report "ERROR: CRC POLYNOMIAL LENGTH MUST BE EQUAL TO CRC LENGTH (SHORTENED VERSION / DON'T PUT MANDATORY MSB '1')" severity failure;
report "ERROR: CRC POLYNOMIAL LENGTH MUST BE EQUAL TO CRC LENGTH (SHORTENED VERSION / DON'T PUT MANDATORY HIGHER POLYNOME '1')" severity failure;
wait;
end process;
end generate CHKCRCP1;
CHKCRCP2 : if CCSDS_RXTX_CRC_POLYNOMIAL(CCSDS_RXTX_CRC_LENGTH*8-1) = '0' generate
process
begin
report "ERROR: CRC POLYNOMIAL LSB MUST BE EQUAL TO '1': " & std_logic'image(CCSDS_RXTX_CRC_POLYNOMIAL(CCSDS_RXTX_CRC_LENGTH*8-1)) severity failure;
report "ERROR: CRC POLYNOMIAL MSB MUST BE EQUAL TO '1': " & std_logic'image(CCSDS_RXTX_CRC_POLYNOMIAL(CCSDS_RXTX_CRC_LENGTH*8-1)) severity failure;
wait;
end process;
end generate CHKCRCP2;
......
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_lfsr
---- Version: 1.0.0
---- Description:
---- Linear Feedback Shift Register
---- Input: none
---- Timing requirements: CCSDS_RXTX_LFSR_DATA_BUS_SIZE+1 clock cycles for valid output data
---- Output: dat_val_o <= "1" / dat_o <= "LFSRSEQUENCE"
---- Ressources requirements: TODO
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- Test ressources:
-- GNURADIO GLFSR block
-- CCSDS parameters
-- Width = 8
-- Mode = Fibonacci ('0')
-- Polynomial = x"A9"
-- Seed = x"FF"
-- Result = "1111111101001000000011101100000010011010"
-- Width = 8
-- Mode = Galois ('1')
-- Polynomial = x"A9"
-- Seed = x"FF"
-- Result = "101001011011000001011000110110"
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx randomizer inputs and outputs
--=============================================================================
entity ccsds_rxtx_lfsr is
generic(
constant CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_RXTX_LFSR_MEMORY_SIZE: integer range 2 to 256 := 8; -- in bits
constant CCSDS_RXTX_LFSR_MODE: std_logic := '0'; -- 0: Fibonacci / 1: Galois
constant CCSDS_RXTX_LFSR_POLYNOMIAL: std_logic_vector := x"A9"; -- Polynomial / MSB <=> lower polynome (needs to be '1')
constant CCSDS_RXTX_LFSR_SEED: std_logic_vector := x"FF" -- Initial Value
);
port(
-- inputs
clk_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_rxtx_lfsr;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_rxtx_lfsr is
-- internal constants
-- internal variable signals
signal lfsr_memory: std_logic_vector(CCSDS_RXTX_LFSR_MEMORY_SIZE-1 downto 0) := CCSDS_RXTX_LFSR_SEED;
-- components instanciation and mapping
begin
-- presynthesis checks
CHKLFSRP0 : if CCSDS_RXTX_LFSR_POLYNOMIAL'length /= CCSDS_RXTX_LFSR_MEMORY_SIZE generate
process
begin
report "ERROR: LFSR_POLYNOMIAL LENGTH MUST BE EQUAL TO MEMORY SIZE (SHORTENED VERSION / DON'T PUT MANDATORY HIGHER POLYNOME '1')" severity failure;
wait;
end process;
end generate CHKLFSRP0;
CHKLFSRP1 : if CCSDS_RXTX_LFSR_MEMORY_SIZE <= 1 generate
process
begin
report "ERROR: LFSR_MEMORY_SIZE MUST BE BIGGER THAN 1" severity failure;
wait;
end process;
end generate CHKLFSRP1;
CHKLFSRP2 : if CCSDS_RXTX_LFSR_SEED'length /= CCSDS_RXTX_LFSR_MEMORY_SIZE generate
process
begin
report "ERROR: LFSR_SEED LENGTH MUST BE EQUAL TO LFSR_MEMORY_SIZE" severity failure;
wait;
end process;
end generate CHKLFSRP2;
CHKLFSRP3 : if CCSDS_RXTX_LFSR_POLYNOMIAL(CCSDS_RXTX_LFSR_MEMORY_SIZE-1) = '0' generate
process
begin
report "ERROR: LFSR POLYNOMIAL MSB MUST BE EQUAL TO 1" severity failure;
wait;
end process;
end generate CHKLFSRP3;
-- internal processing
--=============================================================================
-- Begin of crcp
-- Compute CRC based on input data
--=============================================================================
-- read: rst_i
-- write: dat_o, dat_val_o
-- r/w: lfsr_memory
LFSRP: process (clk_i)
variable output_pointer: integer range -1 to (CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1) := CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1;
variable feedback_register: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
lfsr_memory <= CCSDS_RXTX_LFSR_SEED;
dat_o <= (others => '0');
dat_val_o <= '0';
output_pointer := CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1;
feedback_register := '0';
else
-- generation is finished
if (output_pointer = -1) then
dat_val_o <= '1';
-- generating sequence
else
dat_val_o <= '0';
-- Fibonacci
if (CCSDS_RXTX_LFSR_MODE = '0') then
dat_o(output_pointer) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
output_pointer := output_pointer - 1;
feedback_register := lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
for i in 0 to CCSDS_RXTX_LFSR_MEMORY_SIZE-2 loop
if (CCSDS_RXTX_LFSR_POLYNOMIAL(i) = '1') then
feedback_register := feedback_register xor lfsr_memory(i);
end if;
end loop;
lfsr_memory <= std_logic_vector(resize(unsigned(lfsr_memory),CCSDS_RXTX_LFSR_MEMORY_SIZE-1)) & feedback_register;
-- Galois
else
dat_o(output_pointer) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
output_pointer := output_pointer - 1;
lfsr_memory(0) <= lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
for i in 1 to CCSDS_RXTX_LFSR_MEMORY_SIZE-1 loop
if (CCSDS_RXTX_LFSR_POLYNOMIAL(i) = '1') then
lfsr_memory(i) <= lfsr_memory(i-1) xor lfsr_memory(CCSDS_RXTX_LFSR_MEMORY_SIZE-1);
else
lfsr_memory(i) <= lfsr_memory(i-1);
end if;
end loop;
end if;
end if;
end if;
end if;
end process;
end structure;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_coder
---- Version: 1.0.0
---- Description:
---- Implementation of standard CCSDS 131.0-B-2
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx coder inputs and outputs
--=============================================================================
entity ccsds_tx_coder is
generic(
constant CCSDS_TX_CODER_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_coder;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_coder is
component ccsds_tx_randomizer is
generic(
CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_synchronizer is
generic(
CCSDS_TX_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
CCSDS_TX_ASM_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal wire_randomizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
signal wire_randomizer_dat_val_o: std_logic;
-- components instanciation and mapping
begin
tx_coder_randomizer_0: ccsds_tx_randomizer
generic map(
CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => dat_val_i,
dat_i => dat_i,
dat_val_o => wire_randomizer_dat_val_o,
dat_o => wire_randomizer_dat_o
);
tx_coder_synchronizer_0: ccsds_tx_synchronizer
generic map(
CCSDS_TX_ASM_LENGTH => CCSDS_TX_CODER_ASM_LENGTH,
CCSDS_TX_ASM_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
);
-- presynthesis checks
-- internal processing
end structure;
......@@ -26,6 +26,7 @@ use ieee.math_real.all;
--=============================================================================
entity ccsds_tx_datalink_layer is
generic (
constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer := 32; -- in bits
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 24; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
......@@ -66,12 +67,28 @@ architecture structure of ccsds_tx_datalink_layer is
dat_val_o: out std_logic
);
end component;
component ccsds_tx_coder is
generic(
CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
CCSDS_TX_CODER_ASM_LENGTH: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- interconnection signals
signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
signal wire_framer_data_valid: std_logic;
signal wire_coder_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8-1 downto 0);
signal wire_coder_data_valid: std_logic;
-- components instanciation and mapping
begin
......@@ -91,13 +108,23 @@ architecture structure of ccsds_tx_datalink_layer is
dat_val_o => wire_framer_data_valid,
dat_o => wire_framer_data
);
tx_datalink_coder_0: ccsds_tx_coder
generic map(
CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8
)
port map(
clk_i => clk_i,
dat_i => wire_framer_data,
dat_val_i => wire_framer_data_valid,
rst_i => rst_i,
dat_val_o => wire_coder_data_valid,
dat_o => wire_coder_data
);
buf_dat_ful_o <= '0';
dat_val_o <= wire_framer_data_valid;
dat_o <= wire_framer_data(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_o <= wire_coder_data_valid;
dat_o <= wire_coder_data(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
-- internal processing
-- constant TX_DATALINK_CCSDS_ASM_SEQUENCE : std_logic_vector(31 downto 0) := "00011010110011111111110000011101"; -- TRAINING SEQUENCE (FOR SYNCHRONIZATION PURPOSES)
end structure;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_randomizer
---- Version: 1.0.0
---- Description:
---- Randomize input data with LFSR output sequence
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx randomizer inputs and outputs
--=============================================================================
entity ccsds_tx_randomizer is
generic(
constant CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_randomizer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_randomizer is
component ccsds_rxtx_lfsr is
generic(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
-- internal variable signals
signal randomizer_sequence: std_logic_vector(CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE-1 downto 0);
signal wire_lfsr_valid: std_logic;
-- components instanciation and mapping
begin
tx_randomizer_lfsr: ccsds_rxtx_lfsr
generic map(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE => CCSDS_TX_RANDOMIZER_DATA_BUS_SIZE
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_val_o => wire_lfsr_valid,
dat_o => randomizer_sequence
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of randp
-- Randomize data using LFSR register
--=============================================================================
-- read: rst_i, dat_val_i, dat_i, randomizer_sequence, wire_lfsr_valid
-- write: dat_o, dat_val_o
-- r/w:
RANDP: process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
dat_o <= (others => '0');
dat_val_o <= '0';
else
if (dat_val_i = '1') and (wire_lfsr_valid = '1') then
dat_val_o <= '1';
dat_o <= dat_i xor randomizer_sequence;
else
dat_val_o <= '0';
end if;
end if;
end if;
end process;
end structure;
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_synchronizer
---- Version: 1.0.0
---- Description:
---- Add an Attached Synchronization Marker to an input frame
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx synchronizer inputs and outputs
--=============================================================================
entity ccsds_tx_synchronizer is
generic(
constant CCSDS_TX_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_ASM_PATTERN: std_logic_vector := "00011010110011111111110000011101"; -- ASM Pattern used
constant CCSDS_TX_ASM_DATA_BUS_SIZE: integer -- in bits
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_synchronizer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_synchronizer is
-- internal constants
-- internal variable signals
-- components instanciation and mapping
begin
-- presynthesis checks
CHKSYNCHRONIZERP0 : if ((CCSDS_TX_ASM_LENGTH*8) /= CCSDS_TX_ASM_PATTERN'length) generate
process
begin
report "ERROR: SYNCHRONIZER ASM LENGTH IS DIFFERENT FROM PATTERN SIZE" severity failure;
wait;
end process;
end generate CHKSYNCHRONIZERP0;
-- internal processing
dat_o(CCSDS_TX_ASM_DATA_BUS_SIZE+CCSDS_TX_ASM_LENGTH*8-1 downto CCSDS_TX_ASM_DATA_BUS_SIZE) <= CCSDS_TX_ASM_PATTERN;
dat_o(CCSDS_TX_ASM_DATA_BUS_SIZE-1 downto 0) <= dat_i;