Commit d0338ebd authored by Guillaume REMBERT's avatar Guillaume REMBERT

Framer parallel footer generation + testbench improvement + coding style review

parent 5d65708a
......@@ -6,7 +6,7 @@
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
......@@ -26,20 +26,21 @@ entity ccsds_rx is
CCSDS_RX_DATA_BUS_SIZE: integer := 32
);
port(
rst_i: in std_logic; -- system reset input
ena_i: in std_logic; -- system enable input
-- inputs
clk_i: in std_logic; -- input samples clock
i_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
q_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
data_next_i: in std_logic; -- next data
data_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
irq_o: out std_logic; -- data ready to be read / IRQ signal
data_valid_o: out std_logic; -- data valid
-- Monitoring outputs
data_buffer_full_o: out std_logic; -- data buffer status indicator
frames_buffer_full_o: out std_logic; -- frames buffer status indicator
bits_buffer_full_o: out std_logic; -- bits buffer status indicator
enabled_o: out std_logic -- enabled status indicator
dat_nxt_i: in std_logic; -- next data
ena_i: in std_logic; -- system enable input
rst_i: in std_logic; -- system reset input
sam_i_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
-- outputs
buf_bit_ful_o: out std_logic; -- bits buffer status indicator
buf_dat_ful_o: out std_logic; -- data buffer status indicator
buf_fra_ful_o: out std_logic; -- frames buffer status indicator
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0); -- received data parallel output
dat_val_o: out std_logic; -- data valid
ena_o: out std_logic; -- enabled status indicator
irq_o: out std_logic -- data ready to be read / IRQ signal
);
end ccsds_rx;
......@@ -51,11 +52,11 @@ architecture structure of ccsds_rx is
port(
clk_i: in std_logic;
rst_i: in std_logic;
data_i: in std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
data_buffer_full_o: out std_logic;
frames_buffer_full_o: out std_logic;
bits_buffer_full_o: out std_logic
dat_i: in std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0);
buf_dat_ful_o: out std_logic;
buf_fra_ful_o: out std_logic;
buf_bit_ful_o: out std_logic
);
end component;
component ccsds_rx_physical_layer is
......@@ -67,9 +68,9 @@ architecture structure of ccsds_rx is
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
i_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
q_samples_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0)
sam_i_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
sam_q_i: in std_logic_vector(CCSDS_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RX_DATA_BUS_SIZE-1 downto 0)
);
end component;
......@@ -85,11 +86,11 @@ begin
port map(
clk_i => wire_clk_m,
rst_i => rst_i,
data_i => wire_data_m,
data_o => data_o,
data_buffer_full_o => data_buffer_full_o,
frames_buffer_full_o => frames_buffer_full_o,
bits_buffer_full_o => bits_buffer_full_o
dat_i => wire_data_m,
dat_o => dat_o,
buf_dat_ful_o => buf_dat_ful_o,
buf_fra_ful_o => buf_fra_ful_o,
buf_bit_ful_o => buf_bit_ful_o
);
rx_physical_layer_1: ccsds_rx_physical_layer
generic map(
......@@ -100,9 +101,9 @@ begin
clk_i => wire_clk_i,
clk_o => wire_clk_m,
rst_i => rst_i,
i_samples_i => i_samples_i,
q_samples_i => q_samples_i,
data_o => wire_data_m
sam_i_i => sam_i_i,
sam_q_i => sam_q_i,
dat_o => wire_data_m
);
--=============================================================================
......@@ -116,10 +117,10 @@ begin
begin
if (ena_i = '1') then
wire_clk_i <= clk_i;
enabled_o <= '1';
ena_o <= '1';
else
wire_clk_i <= '0';
enabled_o <= '0';
ena_o <= '0';
end if;
end process;
end structure;
......@@ -6,7 +6,7 @@
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
......@@ -25,13 +25,15 @@ entity ccsds_rx_datalink_layer is
CCSDS_RX_DATALINK_DATA_BUS_SIZE: integer := 32
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
rst_i: in std_logic;
data_i: in std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0);
data_buffer_full_o: out std_logic;
frames_buffer_full_o: out std_logic;
bits_buffer_full_o: out std_logic
-- outputs
buf_bit_ful_o: out std_logic;
buf_dat_ful_o: out std_logic;
buf_fra_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RX_DATALINK_DATA_BUS_SIZE-1 downto 0)
);
end ccsds_rx_datalink_layer;
......@@ -40,12 +42,12 @@ architecture rtl of ccsds_rx_datalink_layer is
-- TEMPORARY NO CHANGE / DUMMY LINKLAYER
begin
data_o <= data_i;
data_buffer_full_o <= '0';
frames_buffer_full_o <= '0';
bits_buffer_full_o <= '0';
dat_o <= dat_i;
buf_dat_ful_o <= '0';
buf_fra_ful_o <= '0';
buf_bit_ful_o <= '0';
DATALINKP : process (clk_i, data_i)
DATALINKP : process (clk_i, dat_i)
begin
end process;
end rtl;
......@@ -6,7 +6,7 @@
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume REMBERT, guillaume.rembert@euryecetelecom.com
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
......@@ -24,16 +24,18 @@ use ieee.std_logic_1164.all;
--=============================================================================
entity ccsds_rx_physical_layer is
generic (
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH : integer := 16;
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE: integer := 32
CCSDS_RX_PHYSICAL_DATA_BUS_SIZE: integer := 32;
CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH : integer := 16
);
port(
-- inputs
clk_i: in std_logic;
clk_o: out std_logic;
rst_i: in std_logic;
i_samples_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
q_samples_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
data_o: out std_logic_vector(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto 0)
sam_i_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
sam_q_i: in std_logic_vector(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0);
-- outputs
clk_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto 0)
);
end ccsds_rx_physical_layer;
......@@ -45,8 +47,8 @@ architecture rtl of ccsds_rx_physical_layer is
-- architecture begin
--=============================================================================
begin
data_o(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH) <= q_samples_i;
data_o(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0) <= i_samples_i;
dat_o(CCSDS_RX_PHYSICAL_DATA_BUS_SIZE-1 downto CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH) <= sam_q_i;
dat_o(CCSDS_RX_PHYSICAL_SIG_QUANT_DEPTH-1 downto 0) <= sam_i_i;
clk_o <= clk_i;
--=============================================================================
-- Begin of physicalp
......@@ -55,7 +57,7 @@ architecture rtl of ccsds_rx_physical_layer is
-- read: clk_i
-- write:
-- r/w:
PHYSICALP : process (clk_i, i_samples_i, q_samples_i)
PHYSICALP : process (clk_i)
begin
end process;
end rtl;
......
......@@ -5,12 +5,13 @@ description = EurySPACE CCSDS RX/TX with wishbone interface
[vhdl]
src_files =
ccsds_rxtx_bench.vhd
ccsds_rxtx_top.vhd
ccsds_rxtx_buffer.vhd
ccsds_rxtx_constants.vhd
ccsds_rxtx_crc.vhd
ccsds_rxtx_functions.vhd
ccsds_rxtx_parameters.vhd
ccsds_rxtx_buffer.vhd
ccsds_rxtx_crc.vhd
ccsds_rxtx_serdes.vhd
ccsds_rxtx_top.vhd
ccsds_rx.vhd
ccsds_rx_datalink_layer.vhd
ccsds_rx_physical_layer.vhd
......@@ -21,17 +22,3 @@ src_files =
ccsds_tx_framer.vhd
ccsds_tx_header.vhd
ccsds_tx_footer.vhd
# ccsds_rxtx_layer_1.vhdl
# ccsds_rxtx_layer_2.vhdl
# ccsds_rxtx_codec_ecc_crc.vhdl
# ccsds_rxtx_codec_ecc_reed_solomon.vhdl
# ccsds_rxtx_codec_ecc_conv_codes.vhdl
# ccsds_rxtx_mapper_gray.vhdl
# ccsds_rxtx_mapper_psk.vhdl
# ccsds_rxtx_mapper_qam.vhdl
# ccsds_rxtx_modulator.vhdl
# ccsds_rxtx_demodulator.vhdl
# ccsds_rxtx_filter_rrc.vhdl
# ccsds_rxtx_estim_symbol_timing.vhdl
# ccsds_rxtx_estim_phase.vhdl
# ccsds_rxtx_filter_rrc.vhdl
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -15,7 +15,6 @@
---- 2016/02/27: initial release
---- 2016/10/20: major corrections and optimizations
-------------------------------
--FIXME: 1 WORD not used for storage
-- libraries used
library ieee;
......@@ -30,15 +29,17 @@ entity ccsds_rxtx_buffer is
CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
nxt_dat_i: in std_logic;
rst_i: in std_logic;
buffer_empty_o: out std_logic;
buffer_full_o: out std_logic;
next_data_i: in std_logic;
data_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
data_valid_i: in std_logic;
data_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
data_valid_o: out std_logic
-- outputs
buf_emp_o: out std_logic;
buf_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_rxtx_buffer;
......@@ -48,10 +49,10 @@ end ccsds_rxtx_buffer;
architecture rtl of ccsds_rxtx_buffer is
-- interconnection signals
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE-1 := 0;
type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE-1 downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
signal buffer_data: buffer_array := (others => (others => '0'));
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
-- components instanciation and mapping
begin
......@@ -59,62 +60,75 @@ architecture rtl of ccsds_rxtx_buffer is
-- internal processing
--=============================================================================
-- Begin of bufferpushp
-- Store valid input data in buffer
-- Begin of bufferpullp
-- Read data from buffer
--=============================================================================
-- read: data_valid_i, rst_i
-- write: buffer_write_pos, buffer_data, wire_buffer_full
-- r/w:
BUFFERPUSH : process (clk_i)
-- read: nxt_dat_i, rst_i, buffer_write_pos, buffer_data
-- write: dat_o, dat_val_o, buf_emp_o
-- r/w: buffer_read_pos
BUFFERPULLP : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
buffer_write_pos <= 0;
buffer_full_o <= '0';
buf_emp_o <= '1';
buffer_read_pos <= 0;
dat_o <= (others => '0');
dat_val_o <= '0';
else
-- check if buffer is full
if ((buffer_write_pos+1) mod CCSDS_RXTX_BUFFER_SIZE = buffer_read_pos) then
buffer_full_o <= '1';
if (buffer_read_pos = buffer_write_pos) then
buf_emp_o <= '1';
dat_val_o <= '0';
else
buffer_full_o <= '0';
if (data_valid_i = '1') then
-- copy data to buffer mem
buffer_data(buffer_write_pos) <= data_i;
buffer_write_pos <= (buffer_write_pos + 1) mod CCSDS_RXTX_BUFFER_SIZE;
buf_emp_o <= '0';
if (nxt_dat_i = '1') then
dat_val_o <= '1';
dat_o <= buffer_data(buffer_read_pos);
if (buffer_read_pos < CCSDS_RXTX_BUFFER_SIZE) then
buffer_read_pos <= (buffer_read_pos + 1);
else
buffer_read_pos <= 0;
end if;
else
dat_val_o <= '0';
end if;
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of bufferpullp
-- Read data from buffer
-- Begin of bufferpushp
-- Store valid input data in buffer
--=============================================================================
-- read: wire_buffer_empty, next_data_i, rst_i
-- write: data_o, buffer_read_pos, data_valid_o, wire_buffer_empty
-- r/w:
BUFFERPULLP : process (clk_i)
-- read: dat_i, dat_val_i, buffer_read_pos, rst_i
-- write: buffer_data, buf_ful_o
-- r/w: buffer_write_pos
BUFFERPUSH : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
buffer_read_pos <= 0;
data_valid_o <= '0';
data_o <= (others => '0');
buffer_empty_o <= '1';
buffer_data <= (others => (others => '0'));
buf_ful_o <= '0';
buffer_write_pos <= 0;
else
-- check if buffer is empty
if (buffer_read_pos = buffer_write_pos) then
buffer_empty_o <= '1';
data_valid_o <= '0';
if (buffer_write_pos < CCSDS_RXTX_BUFFER_SIZE) then
if (buffer_read_pos = (buffer_write_pos+1)) then
buf_ful_o <= '1';
else
buf_ful_o <= '0';
if (dat_val_i = '1') then
buffer_data(buffer_write_pos) <= dat_i;
buffer_write_pos <= (buffer_write_pos + 1);
end if;
end if;
else
buffer_empty_o <= '0';
if (next_data_i = '1') then
data_valid_o <= '1';
data_o <= buffer_data(buffer_read_pos);
buffer_read_pos <= (buffer_read_pos + 1) mod CCSDS_RXTX_BUFFER_SIZE;
if (buffer_read_pos = 0) then
buf_ful_o <= '1';
else
data_valid_o <= '0';
buf_ful_o <= '0';
if (dat_val_i = '1') then
buffer_data(buffer_write_pos) <= dat_i;
buffer_write_pos <= 0;
end if;
end if;
end if;
end if;
......
This diff is collapsed.
......@@ -23,7 +23,7 @@ use ieee.numeric_std.all;
use ieee.math_real.all;
package ccsds_rxtx_functions is
-- synthesable functions
-- synthetizable functions
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector;
-- simulation / testbench only functions
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
......@@ -35,8 +35,8 @@ package body ccsds_rxtx_functions is
variable result: std_logic_vector(input'RANGE);
alias output: std_logic_vector(input'REVERSE_RANGE) is input;
begin
for i in output'RANGE loop
result(i) := output(i);
for vector_pointer in output'RANGE loop
result(vector_pointer) := output(vector_pointer);
end loop;
return result;
end;
......@@ -51,11 +51,11 @@ package body ccsds_rxtx_functions is
result := std_logic_vector(to_unsigned(integer(rand),vector_size));
else
uniform(seed1, seed2, rand);
for i in 0 to vector_size-1 loop
for vector_pointer in 0 to vector_size-1 loop
uniform(seed1, seed2, rand);
rand := rand*(2**(real(32)-1.0));
temp := std_logic_vector(to_unsigned(integer(rand),32));
result(i) := temp(i mod 32);
result(vector_pointer) := temp(vector_pointer mod 32);
end loop;
end if;
end sim_generate_random_std_logic_vector;
......
......@@ -29,7 +29,6 @@ package ccsds_rxtx_parameters is
-- TX CONFIGURATION
constant TX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of TX at startup
constant TX_SYSTEM_AUTO_EXTERNAL: std_logic := '0';--Automatic configuration of RX to use external clock and data
constant TX_SYSTEM_DATA_BUFFER_SIZE: integer := 64;--TX parallel input data words buffer size (words of RXTX_SYSTEM_WB_DATA_BUS_SIZE bits)
-- LAYERS CONFIGURATION
-- APPLICATION LAYER
-- PRESENTATION LAYER
......@@ -37,12 +36,6 @@ package ccsds_rxtx_parameters is
-- TRANSPORT LAYER
-- NETWORK LAYER
-- DATALINK LAYER
-- CCSDS HEADERS
constant TX_DATALINK_CCSDS_HEADERS_ENABLE: boolean := true;
constant TX_DATALINK_CCSDS_HEADERS_SPACECRAFT_ID: std_logic_vector(9 downto 0) := "1000000001"; -- INITIAL SPACECRAFT ID (SPECIFIC WORD / 10 BITS)
constant TX_DATALINK_CCSDS_HEADERS_FRAME_INIT_NUM: std_logic_vector(18 downto 0) := (others => '0'); -- INITIAL FRAME NUMBER (INTEGER / MAX 19 BITS VALUE)
constant TX_DATALINK_CCSDS_HEADERS_JAM_PAYLOAD: std_logic_vector(10 downto 0) := "11000000011"; -- JAM PAYLOAD (SPECIFIC WORD / 11 BITS)
constant TX_DATALINK_CCSDS_ASM_SEQUENCE : std_logic_vector(31 downto 0) := "00011010110011111111110000011101"; -- TRAINING SEQUENCE (FOR SYNCHRONIZATION PURPOSES)
-- PHYSICAL LAYER
constant TX_PHYS_SIG_QUANT_DEPTH: integer := 16;-- DIGITAL PROCESSING QUANTIFICATION DEPTH IN BITS NUMBER
constant RX_PHYS_SIG_QUANT_DEPTH: integer := 16;-- DIGITAL PROCESSING QUANTIFICATION DEPTH IN BITS NUMBER
......
......@@ -14,6 +14,7 @@
-------------------------------
---- Changes list:
---- 2015/11/18: initial release
---- 2016/10/27: review + add ser2par
-------------------------------
-- libraries used
......@@ -27,18 +28,22 @@ use work.ccsds_rxtx_parameters.all;
--=============================================================================
entity ccsds_rxtx_serdes is
generic (
CCSDS_RXTX_SERDES_DEPTH : integer := RXTX_SYSTEM_WB_DATA_BUS_SIZE
CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
-- inputs
clk_i: in std_logic; -- parallel input data clock
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel input data
dat_par_val_i: in std_logic; -- parallel data valid indicator
dat_ser_i: in std_logic; -- serial input data
dat_ser_val_i: in std_logic; -- serial data valid indicator
rst_i: in std_logic; -- system reset input
clk_par_i: in std_logic; -- parallel input data clock
clk_ser_i: in std_logic; -- serial input data clock
clk_par_o: out std_logic; -- parallel output data clock
clk_ser_o: out std_logic; -- serial output data clock
data_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel input data
data_ser_i: in std_logic; -- serial input data
data_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel output data
data_ser_o: out std_logic -- serial output data
-- outputs
bus_o: out std_logic; -- par2ser busy indicator
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel output data
dat_par_val_o: out std_logic; -- parallel output data valid indicator
dat_ser_o: out std_logic; -- serial output data
dat_ser_val_o: out std_logic -- serial output data valid indicator
);
end ccsds_rxtx_serdes;
......@@ -46,52 +51,102 @@ end ccsds_rxtx_serdes;
-- architecture declaration / internal processing
--=============================================================================
architecture rtl of ccsds_rxtx_serdes is
--=============================================================================
-- architecture begin
--=============================================================================
-- internal variable signals
signal wire_busy: std_logic := '0';
signal wire_data_par_valid: std_logic := '0';
signal wire_data_ser_valid: std_logic := '0';
signal serial_data_pointer: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
signal parallel_data_pointer: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
begin
-- components instanciation and mapping
bus_o <= wire_busy;
dat_par_val_o <= wire_data_par_valid;
dat_ser_val_o <= wire_data_ser_valid;
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of par2serp
-- Serialization of parrallel data received starting with MSB
-- Serialization of parallel data received starting with MSB
--=============================================================================
-- read: clk_par_i, rst_i, data_par_i
-- write: data_ser_o
-- r/w:
PAR2SERP : process (clk_par_i)
variable serdes_pnt: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
-- read: clk_i, rst_i, dat_par_i, dat_par_val_i
-- write: dat_ser_o, wire_data_ser_valid, wire_busy
-- r/w: parallel_data_pointer
PAR2SERP : process (clk_i)
variable serdes_memory: std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_par_i) then
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- reset all
serdes_pnt := CCSDS_RXTX_SERDES_DEPTH-1;
clk_ser_o <= '0';
data_ser_o <= '0';
wire_busy <= '0';
dat_ser_o <= '0';
wire_data_ser_valid <= '0';
parallel_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
serdes_memory := (others => '0');
else
-- generate a dynamic bus position pointer
if (serdes_pnt = 0) then
serdes_pnt := CCSDS_RXTX_SERDES_DEPTH-1;
if (dat_par_val_i = '1') and (parallel_data_pointer = CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
serdes_memory := dat_par_i;
-- serialise data on output_bus
dat_ser_o <= dat_par_i(parallel_data_pointer);
-- decrement position pointer
parallel_data_pointer <= (parallel_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
wire_data_ser_valid <= '1';
else
serdes_pnt := serdes_pnt - 1;
if (parallel_data_pointer /= CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
-- serialise data on output_bus
dat_ser_o <= serdes_memory(parallel_data_pointer);
-- decrement position pointer
parallel_data_pointer <= (parallel_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
wire_data_ser_valid <= '1';
else
-- nothing to do
wire_busy <= '0';
wire_data_ser_valid <= '0';
end if;
end if;
-- serialise data on output_bus
data_ser_o <= data_par_i(serdes_pnt);
end if;
end if;
end process;
--=============================================================================
-- Begin of ser2parp
-- Serialization of parrallel data received
-- Parallelization of serial data received
--=============================================================================
-- read: clk_par_i, rst_i
-- write:
-- r/w:
-- SER2PARP : process (clk_ser_i)
-- begin
-- data_o <= i_samples_i(0);
-- clk_o <= clk_i;
-- end process;
-- read: clk_i, rst_i, dat_ser_i, dat_ser_val_i
-- write: dat_par_o, wire_data_par_valid
-- r/w: serial_data_pointer
SER2PARP : process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- reset all
dat_par_o <= (others => '0');
wire_data_par_valid <= '0';
serial_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
else
if (dat_ser_val_i = '1') then
-- serialise data on output_bus
dat_par_o(serial_data_pointer) <= dat_ser_i;
if (serial_data_pointer = 0) then
wire_data_par_valid <= '1';
else
wire_data_par_valid <= '0';
end if;
-- decrement position pointer
serial_data_pointer <= (serial_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
else
wire_data_par_valid <= '0';
end if;
end if;
end if;
end process;
end rtl;
--=============================================================================
-- architecture end
......
This diff is collapsed.
......@@ -25,24 +25,26 @@ use ieee.std_logic_1164.all;
--=============================================================================
entity ccsds_tx is
generic (
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer;
CCSDS_TX_DATA_BUS_SIZE: integer
CCSDS_TX_DATA_BUS_SIZE: integer;
CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
);
port(
rst_i: in std_logic; -- system reset input
ena_i: in std_logic; -- system enable input
-- inputs
clk_i: in std_logic; -- transmitted data clock
input_sel_i: in std_logic; -- parallel / serial input selection
data_valid_i: in std_logic; -- transmitted data valid input
data_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0); -- transmitted parallel data input
data_ser_i: in std_logic; -- transmitted serial data input
dat_par_i: in std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0); -- transmitted parallel data input
dat_ser_i: in std_logic; -- transmitted serial data input
dat_val_i: in std_logic; -- transmitted data valid input
ena_i: in std_logic; -- system enable input
in_sel_i: in std_logic; -- parallel / serial input selection
rst_i: in std_logic; -- system reset input
-- outputs
buf_bit_ful_o: out std_logic; -- bits buffer status indicator
buf_dat_ful_o: out std_logic; -- data buffer status indicator
buf_fra_ful_o: out std_logic; -- frames buffer status indicator
clk_o: out std_logic; -- output samples clock
i_samples_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
q_samples_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- quadrature-phased parallel complex samples
data_buffer_full_o: out std_logic; -- data buffer status indicator
frames_buffer_full_o: out std_logic; -- frames buffer status indicator
bits_buffer_full_o: out std_logic; -- bits buffer status indicator
enabled_o: out std_logic -- enabled status indicator
ena_o: out std_logic; -- enabled status indicator
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0) -- quadrature-phased parallel complex samples
);
end ccsds_tx;
......@@ -59,13 +61,13 @@ architecture structure of ccsds_tx is
clk_o: out std_logic;
rst_i: in std_logic;
ena_i: in std_logic;
enabled_o: out std_logic;
input_sel_i: in std_logic;
data_par_i: in std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
data_ser_i: in std_logic;
data_valid_i: in std_logic;
data_valid_o: out std_logic;
data_o: out std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0)
ena_o: out std_logic;
in_sel_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
dat_ser_i: in std_logic;
dat_val_i: in std_logic;
dat_val_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0)
);
end component;
component ccsds_tx_datalink_layer is
......@@ -75,13 +77,13 @@ architecture structure of ccsds_tx is
port(
clk_i: in std_logic;
rst_i: in std_logic;
data_valid_i: in std_logic;
data_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);