Commit d697581b authored by Guillaume REMBERT's avatar Guillaume REMBERT

Update external cores used (mor1k/uart/...) + fusesoc latest version CAPI

parent e8c1492a
`include "timescale.v"
`include "euryspace-defines.v"
module euryspace_tb;
......@@ -8,8 +7,13 @@ module euryspace_tb;
// Boot ROM selection
//
////////////////////////////////////////////////////////////////////////
localparam BOOTROM_FILE = "../src/euryspace/sw/clear_r3_and_jump_to_0x100.vh";
//localparam BOOTROM_FILE = "../src/euryspace/sw/spi_uimage_loader.vh";
localparam BOOTROM_FILE = "../src/euryspace_0/sw/clear_r3_and_jump_to_0x100.vh";
//localparam BOOTROM_FILE = "../src/euryspace_0/sw/spi_uimage_loader.vh";
/*
When the SPI uimage loader is used, the following parameter can be
set to provide alternative SPI Flash contents
*/
parameter spi_flash_file = "../src/euryspace_0/bench/spi_image.vh";
reg clk = 0;
reg rst_n = 0;
......
......@@ -7,14 +7,12 @@ set_location_assignment PIN_R8 -to sys_clk_pad_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk_pad_i
#
# UART0: PINS GND <-> GPIO_120 (n°23) / RX <-> GPIO_124 (n°27) / TX <-> GPIO_126 (n°29)
# UART0: PINS RX <-> GPIO_124 (n°27) / TX <-> GPIO_126 (n°29)
#
set_location_assignment PIN_N15 -to uart0_srx_pad_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i
set_location_assignment PIN_L14 -to uart0_stx_pad_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o
set_location_assignment PIN_P15 -to uart0_gnd_pad_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_gnd_pad_o
#
# CCSDS_RXTX0: PINS
......@@ -24,14 +22,14 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_gnd_pad_o
#set_location_assignment PIN_E1 -to ccsds_rxtx0_rx_clk_i
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_clk_i
#Switch 0 as i serial samples
#set_location_assignment PIN_M1 -to ccsds_rxtx0_rx_i_samples_ser_i
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_i_samples_ser_i
#set_location_assignment PIN_M1 -to ccsds_rxtx0_rx_sam_i_i
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_sam_i_i
#Switch 1 as q serial samples
#set_location_assignment PIN_T8 -to ccsds_rxtx0_rx_q_samples_ser_i
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_q_samples_ser_i
#LED 0 as RX ok
set_location_assignment PIN_A15 -to ccsds_rxtx0_rx_ok_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_ok_o
#set_location_assignment PIN_T8 -to ccsds_rxtx0_rx_sam_q_i
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_sam_q_i
#LED 0 as RX enabled
set_location_assignment PIN_A15 -to ccsds_rxtx0_rx_ena_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_ena_o
#LED 1 as demodulated data clk
#set_location_assignment PIN_A13 -to ccsds_rxtx0_rx_clk_o
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_clk_o
......@@ -43,23 +41,23 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_rx_ok_o
set_location_assignment PIN_D3 -to ccsds_rxtx0_tx_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_clk_i
#GPIO_01 as external serial data input
set_location_assignment PIN_C3 -to ccsds_rxtx0_tx_data_ser_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_data_ser_i
#GPIO_O27 as valid samples output
set_location_assignment PIN_E10 -to ccsds_rxtx0_tx_samples_valid_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_samples_valid_o
#GPIO_O29 as serial i samples output
set_location_assignment PIN_B11 -to ccsds_rxtx0_tx_i_samples_ser_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_i_samples_ser_o
#GPIO_O31 as serial q samples output
set_location_assignment PIN_D11 -to ccsds_rxtx0_tx_q_samples_ser_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_q_samples_ser_o
set_location_assignment PIN_C3 -to ccsds_rxtx0_tx_dat_ser_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_dat_ser_i
#GPIO_O27 as ??
#set_location_assignment PIN_E10 -to ccsds_rxtx0_tx_sam_val_o
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_samples_valid_o
#GPIO_O29 as LSB i samples output
set_location_assignment PIN_B11 -to ccsds_rxtx0_tx_sam_i_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_sam_i_o[0]
#GPIO_O31 as LSB q samples output
set_location_assignment PIN_D11 -to ccsds_rxtx0_tx_sam_q_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_sam_q_o[0]
#GPIO_O33 as samples clk output
set_location_assignment PIN_B12 -to ccsds_rxtx0_tx_clk_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_clk_o
#LED 7 as TX ok
set_location_assignment PIN_L3 -to ccsds_rxtx0_tx_ok_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_ok_o
#LED 7 as TX enabled
set_location_assignment PIN_L3 -to ccsds_rxtx0_tx_ena_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ccsds_rxtx0_tx_ena_o
#
# GPIO0 => LEDS
......@@ -202,8 +200,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_pad_o
set_location_assignment PIN_R4 -to sdram_clk_pad_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o
#ADC
#set_location_assignment PIN_B10 -to spi1_mosi_o
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi1_mosi_o
......@@ -229,6 +225,3 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk_pad_o
#GPIO_2_IN[0] PIN_E15
#GPIO_2_IN[1] PIN_E16
#GPIO_2_IN[2] PIN_M16
......@@ -5,15 +5,15 @@ depend =
altera_virtual_jtag
ccsds_rxtx
gpio
i2c
jtag_tap
mor1kx-3.1
i2c-1.14
jtag_tap-1.13
mor1kx-4.1
or1k_bootloaders-0.9
simple_spi
uart16550-1.5
simple_spi-1.6
uart16550-1.5.4
wb_intercon-1.0
wb_ram
wb_sdram_ctrl
wb_ram-1.0
wb_sdram_ctrl-r2
simulators =
icarus
......@@ -28,8 +28,6 @@ src_files =
include_files =
rtl/verilog/include/euryspace-defines.v
rtl/verilog/include/timescale.v
rtl/verilog/include/uart_defines.v
rtl/verilog/wb_intercon.vh
sw/spi_uimage_loader.vh
sw/clear_r3_and_jump_to_0x100.vh
......@@ -43,10 +41,22 @@ tb_include_files =
bench/test-defines.v
[icarus]
depend = elf-loader jtag_vpi mt48lc16m16a2 s25fl064p-1.7 vlog_tb_utils
depend = elf-loader jtag_vpi-r2 mt48lc16m16a2 s25fl064p-1.7 vlog_tb_utils-1.0
iverilog_options = -DICARUS_SIM -DSIM -DSPEEDSIM
[modelsim]
depend = elf-loader jtag_vpi mt48lc16m16a2 s25fl064p-1.7 vlog_tb_utils
vlog_options = +define+SIM +define+MODELSIM_SIM
depend = elf-loader jtag_vpi-r2 mt48lc16m16a2 s25fl064p-1.7 vlog_tb_utils-1.0
vlog_options = +define+SIM +define+MODELSIM_SIM -timescale 1ns/1ps
vsim_options = -L altera_mf_ver -L altera_mf
[parameter bootrom_file]
datatype = file
description = Initial boot ROM contents (in Verilog hex format)
paramtype = vlogparam
scope = private
[parameter spi_flash_file]
datatype = file
description = Initial SPI Flash contents (in Verilog hex format)
paramtype = vlogparam
scope = private
......@@ -2,7 +2,6 @@ SAPI=1
[main]
name = euryspace
description = "EurySPACE system - Altera/Terasic DE0-Nano board"
backend = quartus
[quartus]
......
......@@ -32,7 +32,6 @@
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
`include "euryspace-defines.v"
module clkgen
......
......@@ -4,14 +4,11 @@
//
// Instantiates modules, depending on ORPSoC defines file
//
// Copyright (C) 2013 Stefan Kristiansson
// <stefan.kristiansson@saunalahti.fi
//
// Based on de1 board by
// Franck Jullien, franck.jullien@gmail.com
// Which probably was based on the or1200-generic board by
// Olof Kindgren, which in turn was based on orpsocv2 boards by
// Julius Baxter.
// Based on work by
// Stefan Kristiansson
// Franck Jullien
// Olof Kindgren
// Julius Baxter
//
//////////////////////////////////////////////////////////////////////
//
......@@ -41,70 +38,66 @@
`include "euryspace-defines.v"
module orpsoc_top #(
parameter BOOTROM_FILE = "../src/euryspace/sw/spi_uimage_loader.vh",
parameter uart0_wb_adr_width = 3,
parameter i2c0_wb_adr_width = 3,
parameter spi0_wb_adr_width = 3,
parameter ccsds_rxtx0_wb_adr_width = 4,
parameter ccsds_rxtx0_rx_samples_width = 16,
parameter ccsds_rxtx0_tx_samples_width = 16,
parameter HV1_SADR = 8'h45
parameter EURYSPACE_BOOTROM_FILE = "../src/euryspace_0/sw/spi_uimage_loader.vh",
parameter EURYSPACE_UART0_WB_ADR_WIDTH = 3,
parameter EURYSPACE_I2C0_WB_ADR_WIDTH = 3,
parameter EURYSPACE_SPI0_WB_ADR_WIDTH = 3,
parameter EURYSPACE_CCSDS_RXTX0_WB_ADR_WIDTH = 4,
parameter EURYSPACE_CCSDS_RXTX0_RX_SAM_WIDTH = 16,
parameter EURYSPACE_CCSDS_RXTX0_TX_SAM_WIDTH = 16,
parameter EURYSPACE_I2C0_SADR = 8'h45
)(
input sys_clk_pad_i,
input rst_n_pad_i,
input sys_clk_pad_i,
input rst_n_pad_i,
`ifdef SIM
output tdo_pad_o,
input tms_pad_i,
input tck_pad_i,
input tdi_pad_i,
output tdo_pad_o,
input tms_pad_i,
input tck_pad_i,
input tdi_pad_i,
`endif
output [1:0] sdram_ba_pad_o,
output [12:0] sdram_a_pad_o,
output sdram_cs_n_pad_o,
output sdram_ras_pad_o,
output sdram_cas_pad_o,
output sdram_we_pad_o,
inout [15:0] sdram_dq_pad_io,
output [1:0] sdram_dqm_pad_o,
output sdram_cke_pad_o,
output sdram_clk_pad_o,
input uart0_srx_pad_i,
output uart0_stx_pad_o,
output uart0_gnd_pad_o,
output [1:0] sdram_ba_pad_o,
output [12:0] sdram_a_pad_o,
output sdram_cs_n_pad_o,
output sdram_ras_pad_o,
output sdram_cas_pad_o,
output sdram_we_pad_o,
inout [15:0] sdram_dq_pad_io,
output [1:0] sdram_dqm_pad_o,
output sdram_cke_pad_o,
output sdram_clk_pad_o,
input uart0_srx_pad_i,
output uart0_stx_pad_o,
`ifdef GPIO0
inout [7:0] gpio0_io,
`endif
`ifdef I2C0
inout i2c0_sda_io,
inout i2c0_scl_io,
inout i2c0_sda_io,
inout i2c0_scl_io,
`endif
`ifdef CCSDS_RXTX0
input [ccsds_rxtx0_rx_samples_width-1:0] ccsds_rxtx0_rx_sam_i_i,
input [ccsds_rxtx0_rx_samples_width-1:0] ccsds_rxtx0_rx_sam_q_i,
input ccsds_rxtx0_rx_clk_i,
output ccsds_rxtx0_rx_ena_o,
output ccsds_rxtx0_rx_irq_o,
input ccsds_rxtx0_tx_dat_ser_i,
input ccsds_rxtx0_tx_clk_i,
output [ccsds_rxtx0_tx_samples_width-1:0] ccsds_rxtx0_tx_sam_i_o,
output [ccsds_rxtx0_tx_samples_width-1:0] ccsds_rxtx0_tx_sam_q_o,
output ccsds_rxtx0_tx_clk_o,
output ccsds_rxtx0_tx_ena_o,
input [EURYSPACE_CCSDS_RXTX0_RX_SAM_WIDTH-1:0] ccsds_rxtx0_rx_sam_i_i,
input [EURYSPACE_CCSDS_RXTX0_RX_SAM_WIDTH-1:0] ccsds_rxtx0_rx_sam_q_i,
input ccsds_rxtx0_rx_clk_i,
output ccsds_rxtx0_rx_ena_o,
input ccsds_rxtx0_tx_dat_ser_i,
input ccsds_rxtx0_tx_clk_i,
output [EURYSPACE_CCSDS_RXTX0_TX_SAM_WIDTH-1:0] ccsds_rxtx0_tx_sam_i_o,
output [EURYSPACE_CCSDS_RXTX0_TX_SAM_WIDTH-1:0] ccsds_rxtx0_tx_sam_q_o,
output ccsds_rxtx0_tx_clk_o,
output ccsds_rxtx0_tx_ena_o,
`endif
`ifdef SPI0
output spi0_sck_o,
output spi0_mosi_o,
input spi0_miso_i,
`ifdef SPI0_SLAVE_SELECTS
output spi0_ss_o
`endif
output spi0_sck_o,
output spi0_mosi_o,
input spi0_miso_i,
output spi0_ss_o
`endif
);
......@@ -259,7 +252,6 @@ mor1kx #(
.OPTION_DCACHE_LIMIT_WIDTH(31),
.FEATURE_DMMU("ENABLED"),
.OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0("CAPPUCCINO"),
......@@ -316,6 +308,19 @@ mor1kx #(
.irq_i(or1k_irq),
.traceport_exec_valid_o (),
.traceport_exec_pc_o (),
.traceport_exec_insn_o (),
.traceport_exec_wbdata_o (),
.traceport_exec_wbreg_o (),
.traceport_exec_wben_o (),
.multicore_coreid_i (32'd0),
.multicore_numcores_i (32'd0),
.snoop_adr_i (32'd0),
.snoop_en_i (1'b0),
.du_addr_i(or1k_dbg_adr_i[15:0]),
.du_stb_i(or1k_dbg_stb_i),
.du_dat_i(or1k_dbg_dat_i),
......@@ -395,11 +400,11 @@ adbg_top dbg_if0 (
//
////////////////////////////////////////////////////////////////////////
localparam WB_BOOTROM_MEM_DEPTH = 1024;
localparam EURYSPACE_WB_BOOTROM_MEM_DEPTH = 1024;
wb_bootrom
#(.DEPTH (WB_BOOTROM_MEM_DEPTH),
.MEMFILE (BOOTROM_FILE))
#(.DEPTH (EURYSPACE_WB_BOOTROM_MEM_DEPTH),
.MEMFILE (EURYSPACE_BOOTROM_FILE))
bootrom
(//Wishbone Master interface
.wb_clk_i (wb_clk),
......@@ -412,7 +417,7 @@ wb_bootrom
assign wb_s2m_rom0_err = 1'b0;
assign wb_s2m_rom0_rty = 1'b0;
////////////////////////////////////////////////////////////////////////
//
// SDRAM Memory Controller
......@@ -439,6 +444,7 @@ wb_sdram_ctrl #(
`endif
.CLK_FREQ_MHZ (100), // sdram_clk freq in MHZ
.POWERUP_DELAY (200), // power up delay in us
.REFRESH_MS (32), // delay between refresh cycles im ms
.WB_PORTS (2), // Number of wishbone ports
.ROW_WIDTH (13), // Row width
.COL_WIDTH (9), // Column width
......@@ -489,16 +495,14 @@ wb_sdram_ctrl0 (
wire uart0_irq;
assign wb_s2m_uart0_err = 0;
assign wb_s2m_uart0_rty = 0;
assign uart0_gnd_pad_o = 1'b0;
uart_top uart16550_0 (
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_uart0_adr[uart0_wb_adr_width-1:0]),
.wb_adr_i (wb_m2s_uart0_adr[EURYSPACE_UART0_WB_ADR_WIDTH-1:0]),
.wb_dat_i (wb_m2s_uart0_dat),
.wb_we_i (wb_m2s_uart0_we),
.wb_stb_i (wb_m2s_uart0_stb),
......@@ -540,14 +544,14 @@ wire sda0_padoen_o;
i2c_master_top
#
(
.DEFAULT_SLAVE_ADDR(HV1_SADR)
.DEFAULT_SLAVE_ADDR(EURYSPACE_I2C0_SADR)
)
i2c0
(
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.arst_i (wb_rst),
.wb_adr_i (wb_m2s_i2c0_adr[i2c0_wb_adr_width-1:0]),
.wb_adr_i (wb_m2s_i2c0_adr[EURYSPACE_I2C0_WB_ADR_WIDTH-1:0]),
.wb_dat_i (wb_m2s_i2c0_dat),
.wb_we_i (wb_m2s_i2c0_we),
.wb_cyc_i (wb_m2s_i2c0_cyc),
......@@ -597,7 +601,7 @@ ccsds_rxtx_top ccsds_rxtx_0 (
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_ccsds_rxtx0_adr[ccsds_rxtx0_wb_adr_width-1:0]),
.wb_adr_i (wb_m2s_ccsds_rxtx0_adr[EURYSPACE_CCSDS_RXTX0_WB_ADR_WIDTH-1:0]),
.wb_dat_i (wb_m2s_ccsds_rxtx0_dat),
.wb_we_i (wb_m2s_ccsds_rxtx0_we),
.wb_stb_i (wb_m2s_ccsds_rxtx0_stb),
......@@ -643,16 +647,12 @@ wire spi0_irq;
//
// Assigns
//
assign wbs_d_spi0_err_o = 0;
assign wbs_d_spi0_rty_o = 0;
assign spi0_hold_n_o = 1;
assign spi0_w_n_o = 1;
simple_spi spi0(
// Wishbone slave interface
.clk_i (wb_clk),
.rst_i (wb_rst),
.adr_i (wb_m2s_spi0_adr[spi0_wb_adr_width-1:0]),
.adr_i (wb_m2s_spi0_adr[EURYSPACE_SPI0_WB_ADR_WIDTH-1:0]),
.dat_i (wb_m2s_spi0_dat),
.we_i (wb_m2s_spi0_we),
.stb_i (wb_m2s_spi0_stb),
......@@ -663,11 +663,7 @@ simple_spi spi0(
// Outputs
.inta_o (spi0_irq),
.sck_o (spi0_sck_o),
`ifdef SPI0_SLAVE_SELECTS
.ss_o (spi0_ss_o),
`else
.ss_o (),
`endif
.mosi_o (spi0_mosi_o),
// Inputs
......@@ -756,7 +752,7 @@ assign or1k_irq[16] = 0;
assign or1k_irq[17] = 0;
assign or1k_irq[18] = 0;
assign or1k_irq[19] = 0;
`ifdef CCSDS_RXTX
`ifdef CCSDS_RXTX0
assign or1k_irq[20] = ccsds_rxtx0_irq;
`else
assign or1k_irq[20] = 0;
......
......@@ -37,10 +37,9 @@
`define ALTERA_JTAG_TAP
`define I2C0
`define SPI0_SLAVE_SELECTS
`define SPI0
`define GPIO0
`define RAM_WB
`define INTGEN
//`define RAM_WB
//`define INTGEN
`define CCSDS_RXTX0
// end of included module defines - keep this comment line here
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