Commit e1ae5264 authored by Guillaume REMBERT's avatar Guillaume REMBERT

Differential coding support + WB burst write support + overflow protection +...

Differential coding support + WB burst write support + overflow protection + idle data insertion indicator
parent 27695e14
This diff is collapsed.
......@@ -36,8 +36,8 @@ entity ccsds_rxtx_buffer is
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_nxt_i: in std_logic;
dat_val_i: in std_logic;
nxt_dat_i: in std_logic;
rst_i: in std_logic;
-- outputs
buf_emp_o: out std_logic;
......@@ -84,7 +84,7 @@ architecture rtl of ccsds_rxtx_buffer is
dat_val_o <= '0';
else
buf_emp_o <= '0';
if (nxt_dat_i = '1') then
if (dat_nxt_i = '1') then
dat_val_o <= '1';
dat_o <= buffer_data(buffer_read_pos);
if (buffer_read_pos < CCSDS_RXTX_BUFFER_SIZE) then
......
......@@ -14,6 +14,7 @@
---- Changes list:
---- 2015/12/28: initial release
---- 2016/10/20: added reverse_std_logic_vector function + rework sim_generate_random_std_logic_vector for > 32 bits vectors
---- 2016/11/17: added convert_boolean_to_std_logic function
-------------------------------
-- libraries used
......@@ -24,6 +25,7 @@ use ieee.math_real.all;
package ccsds_rxtx_functions is
-- synthetizable functions
function convert_boolean_to_std_logic(input: in boolean) return std_logic;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector;
-- simulation / testbench only functions
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
......@@ -31,6 +33,15 @@ end ccsds_rxtx_functions;
package body ccsds_rxtx_functions is
function convert_boolean_to_std_logic(input: in boolean) return std_logic is
begin
if (input = true) then
return '1';
else
return '0';
end if;
end convert_boolean_to_std_logic;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(input'RANGE);
alias output: std_logic_vector(input'REVERSE_RANGE) is input;
......
......@@ -25,7 +25,7 @@ use ieee.std_logic_1164.all;
entity ccsds_rxtx_oversampler is
generic(
constant CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer := 4;
constant CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: std_logic := '0';
constant CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: boolean := false;
constant CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
);
port(
......@@ -83,7 +83,7 @@ architecture structure of ccsds_rxtx_oversampler is
else
if (sam_val_i = '1') then
sam_val_o <= '1';
if (CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING = '1') then
if (CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING = true) then
if (samples_counter <= 0) then
sam_o <= (others => '0');
samples_counter := CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO-1;
......
......@@ -25,10 +25,10 @@ package ccsds_rxtx_parameters is
constant RXTX_SYSTEM_WB_DATA_BUS_SIZE: integer := 32;-- Wishbone slave data bus size (bits)
constant RXTX_SYSTEM_WB_ADDR_BUS_SIZE: integer := 4;-- Wishbone slave address bus size (bits)
-- RX CONFIGURATION
constant RX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of RX at startup
constant RX_SYSTEM_AUTO_ENABLED: boolean := true;--Automatic activation of RX at startup
-- TX CONFIGURATION
constant TX_SYSTEM_AUTO_ENABLED: std_logic := '1';--Automatic activation of TX at startup
constant TX_SYSTEM_AUTO_EXTERNAL: std_logic := '0';--Automatic configuration of RX to use external clock and data
constant TX_SYSTEM_AUTO_ENABLED: boolean := true;--Automatic activation of TX at startup
constant TX_SYSTEM_AUTO_EXTERNAL: boolean := false;--Automatic configuration of TX to use external clock and data
-- LAYERS CONFIGURATION
-- APPLICATION LAYER
-- PRESENTATION LAYER
......
This diff is collapsed.
......@@ -26,9 +26,10 @@ use ieee.std_logic_1164.all;
entity ccsds_tx is
generic (
constant CCSDS_TX_BITS_PER_SYMBOL: integer := 1;
constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=PSK / 2=GMSK
constant CCSDS_TX_BUFFER_SIZE: integer := 16; -- max number of words stored for burst write at full speed when datalinklayer is full
constant CCSDS_TX_MODULATION_TYPE: integer := 1; -- 1=QAM/QPSK / 2=GMSK
constant CCSDS_TX_DATA_BUS_SIZE: integer;
constant CCSDS_TX_OVERSAMPLING_RATIO: integer := 4;
constant CCSDS_TX_OVERSAMPLING_RATIO: integer := 4; -- symbols to samples over-sampling ratio
constant CCSDS_TX_PHYS_SIG_QUANT_DEPTH : integer
);
port(
......@@ -41,8 +42,10 @@ entity ccsds_tx is
in_sel_i: in std_logic; -- parallel / serial input selection
rst_i: in std_logic; -- system reset input
-- outputs
buf_ful_o: out std_logic; -- buffer full indicator
clk_o: out std_logic; -- output samples clock
ena_o: out std_logic; -- enabled status indicator
idl_o: out std_logic; -- idle data insertion indicator
sam_i_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0); -- in-phased parallel complex samples
sam_q_o: out std_logic_vector(CCSDS_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0) -- quadrature-phased parallel complex samples
);
......@@ -76,6 +79,23 @@ architecture structure of ccsds_tx is
dat_o: out std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0)
);
end component;
component ccsds_rxtx_buffer is
generic(
constant CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer;
constant CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_nxt_i: in std_logic;
rst_i: in std_logic;
buf_emp_o: out std_logic;
buf_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_datalink_layer is
generic(
CCSDS_TX_DATALINK_DATA_BUS_SIZE : integer
......@@ -87,7 +107,9 @@ architecture structure of ccsds_tx is
dat_val_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0)
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_tx_physical_layer is
......@@ -109,15 +131,18 @@ architecture structure of ccsds_tx is
);
end component;
signal wire_data_valid_m: std_logic;
signal wire_data_valid_d: std_logic;
signal wire_data_m: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_data_d: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_dat_nxt_buf: std_logic;
signal wire_dat_val_buf: std_logic;
signal wire_dat_val_dat: std_logic;
signal wire_dat_val_man: std_logic;
signal wire_dat_buf: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_dat_dat: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_dat_man: std_logic_vector(CCSDS_TX_DATA_BUS_SIZE-1 downto 0);
signal wire_clk_dat: std_logic;
signal wire_clk_sam: std_logic;
signal wire_clk_sym: std_logic;
signal wire_clk_bit: std_logic;
signal wire_rst_m: std_logic;
signal wire_rst_man: std_logic;
begin
tx_manager_0: ccsds_tx_manager
......@@ -140,8 +165,24 @@ begin
dat_val_i => dat_val_i,
dat_par_i => dat_par_i,
dat_ser_i => dat_ser_i,
dat_val_o => wire_data_valid_m,
dat_o => wire_data_m
dat_val_o => wire_dat_val_man,
dat_o => wire_dat_man
);
tx_buffer_0: ccsds_rxtx_buffer
generic map(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE => CCSDS_TX_DATA_BUS_SIZE,
CCSDS_RXTX_BUFFER_SIZE => CCSDS_TX_BUFFER_SIZE
)
port map(
clk_i => wire_clk_dat,
rst_i => rst_i,
dat_nxt_i => wire_dat_nxt_buf,
dat_val_i => wire_dat_val_man,
dat_i => wire_dat_man,
dat_val_o => wire_dat_val_buf,
-- buf_emp_o => ,
buf_ful_o => buf_ful_o,
dat_o => wire_dat_buf
);
tx_datalink_layer_0: ccsds_tx_datalink_layer
generic map(
......@@ -151,10 +192,12 @@ begin
clk_dat_i => wire_clk_dat,
clk_bit_i => wire_clk_bit,
rst_i => rst_i,
dat_val_i => wire_data_valid_m,
dat_i => wire_data_m,
dat_val_o => wire_data_valid_d,
dat_o => wire_data_d
dat_val_i => wire_dat_val_buf,
dat_i => wire_dat_buf,
dat_val_o => wire_dat_val_dat,
dat_nxt_o => wire_dat_nxt_buf,
dat_o => wire_dat_dat,
idl_o => idl_o
);
tx_physical_layer_0: ccsds_tx_physical_layer
generic map(
......@@ -170,8 +213,8 @@ begin
rst_i => rst_i,
sam_i_o => sam_i_o,
sam_q_o => sam_q_o,
dat_i => wire_data_d,
dat_val_i => wire_data_valid_d
dat_i => wire_dat_dat,
dat_val_i => wire_dat_val_dat
);
clk_o <= wire_clk_sam;
end structure;
......@@ -41,7 +41,9 @@ entity ccsds_tx_datalink_layer is
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
dat_nxt_o: out std_logic;
dat_val_o: out std_logic;
idl_o: out std_logic
);
end ccsds_tx_datalink_layer;
......@@ -62,7 +64,9 @@ architecture structure of ccsds_tx_datalink_layer is
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic
dat_val_o: out std_logic;
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_tx_coder is
......@@ -106,7 +110,9 @@ architecture structure of ccsds_tx_datalink_layer is
dat_val_i => dat_val_i,
dat_i => dat_i,
dat_val_o => wire_framer_data_valid,
dat_o => wire_framer_data
dat_nxt_o => dat_nxt_o,
dat_o => wire_framer_data,
idl_o => idl_o
);
tx_datalink_coder_0: ccsds_tx_coder
generic map(
......
......@@ -26,7 +26,7 @@ entity ccsds_tx_filter is
generic(
constant CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer; -- in bits
constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_FILTER_OFFSET_PSK: std_logic := '1';
constant CCSDS_TX_FILTER_OFFSET_PSK: boolean := true;
constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer
);
......@@ -51,7 +51,7 @@ architecture structure of ccsds_tx_filter is
component ccsds_rxtx_oversampler is
generic(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: std_logic;
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: boolean;
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
);
port(
......@@ -94,7 +94,7 @@ architecture structure of ccsds_tx_filter is
tx_oversampler_i_0: ccsds_rxtx_oversampler
generic map(
CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => '0',
CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => false,
CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
)
port map(
......
......@@ -36,7 +36,7 @@ entity ccsds_tx_framer is
constant CCSDS_TX_FRAMER_DATA_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_FOOTER_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_HEADER_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO: integer := 16 -- activated max framer parallelism speed ratio / 1 = full speed / 2 = wishbone bus max speed / ... / 32 = external serial data
constant CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO: integer := 16 -- activated max framer parallelism speed ratio / 1 = full speed / 2 = wishbone bus non-pipelined write max speed / ... / CCSDS_TX_FRAMER_DATA_BUS_SIZE = external serial data
);
port(
-- inputs
......@@ -46,7 +46,9 @@ entity ccsds_tx_framer is
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic
dat_nxt_o: out std_logic;
dat_val_o: out std_logic;
idl_o: out std_logic
);
end ccsds_tx_framer;
......@@ -249,7 +251,7 @@ architecture structure of ccsds_tx_framer is
-- Generate next_frame, start next header generation
--=============================================================================
-- read: dat_val_i, rst_i
-- write: wire_header_next, reg_current_frame, reg_next_frame
-- write: wire_header_next, reg_current_frame, reg_next_frame, dat_nxt_o, idl_o
-- r/w:
FRAMERGENERATEP: process (clk_i)
variable next_frame_write_pos: integer range 0 to (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1 := (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
......@@ -264,6 +266,8 @@ architecture structure of ccsds_tx_framer is
wire_header_next <= '0';
next_frame_write_pos := (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
frame_output_counter := 0;
idl_o <= '0';
dat_nxt_o <= '0';
else
-- valid data is presented
if (dat_val_i = '1') then
......@@ -273,34 +277,58 @@ architecture structure of ccsds_tx_framer is
reg_current_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto CCSDS_TX_FRAMER_DATA_BUS_SIZE) <= reg_next_frame;
-- time to start frame computation
if (frame_output_counter = 0) then
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*8*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
wire_header_next <= '1';
wire_header_idle <= '0';
-- signal a frame ready for computation
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*8*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
wire_header_next <= '1';
wire_header_idle <= '0';
idl_o <= '0';
-- source data rate overflow / stop buffer output
else
dat_nxt_o <= '0';
end if;
else
wire_header_next <= '0';
frame_output_counter := frame_output_counter - 1;
current_frame_ready := '1';
-- signal a frame ready for computation
if (current_frame_ready = '0') then
wire_header_next <= '0';
current_frame_ready := '1';
-- source data rate overflow
else
dat_nxt_o <= '0';
end if;
end if;
next_frame_write_pos := CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE-1;
-- filling next frame
else
-- filling next frame
reg_next_frame(next_frame_write_pos*CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto (next_frame_write_pos-1)*CCSDS_TX_FRAMER_DATA_BUS_SIZE) <= dat_i;
next_frame_write_pos := next_frame_write_pos-1;
-- time to start frame computation
if (frame_output_counter = 0) then
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
-- no frame is ready
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
-- a frame is ready
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
dat_nxt_o <= '1';
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
-- no frame is ready / inserting idle data
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
idl_o <= '1';
-- a frame is ready
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
idl_o <= '0';
end if;
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
dat_nxt_o <= '0';
end if;
else
-- stop data before overflow
if (next_frame_write_pos = 1) and (current_frame_ready = '1') then
dat_nxt_o <= '0';
end if;
frame_output_counter := frame_output_counter - 1;
wire_header_next <= '0';
end if;
......@@ -309,14 +337,20 @@ architecture structure of ccsds_tx_framer is
else
-- time to start frame computation
if (frame_output_counter = 0) then
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
dat_nxt_o <= '1';
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
idl_o <= '1';
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
idl_o <= '0';
end if;
end if;
else
wire_header_next <= '0';
......
......@@ -3,7 +3,7 @@
---- Design Name: ccsds_tx_mapper
---- Version: 1.0.0
---- Description:
---- TBD
---- Implementation of standard CCSDS 401.0-B
-------------------------------
---- Author(s):
---- Guillaume REMBERT
......@@ -13,21 +13,24 @@
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
---- 2016/11/17: added differential coder
-------------------------------
--TODO: Gray coder
--TODO: Differential coder
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx mapper inputs and outputs
--=============================================================================
entity ccsds_tx_mapper is
generic(
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer := 1;
constant CCSDS_TX_MAPPER_MODULATION_TYPE: integer := 1; -- 1=nPSK / 2=BPSK
constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer := 1; -- For QAM - 1 bit/symbol <=> QPSK/4-QAM - 2 bits/symbol <=> 16-QAM - 3 bits/symbol <=> 64-QAM - ... - N bits/symbol <=> 2^(N*2)-QAM
constant CCSDS_TX_MAPPER_DIFFERENTIAL_CODER: boolean := false; -- Differential coder activation
constant CCSDS_TX_MAPPER_GRAY_CODER: std_logic := '1'; -- Gray coder activation
constant CCSDS_TX_MAPPER_MODULATION_TYPE: integer := 1; -- 1=QPSK/QAM - 2=BPSK
constant CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer -- in bits
);
port(
......@@ -51,6 +54,7 @@ architecture structure of ccsds_tx_mapper is
constant MAPPER_SYMBOL_NUMBER_PER_CHANNEL: integer := CCSDS_TX_MAPPER_DATA_BUS_SIZE*CCSDS_TX_MAPPER_MODULATION_TYPE/(2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
-- internal variable signals
signal symbol_counter: integer range 1 to MAPPER_SYMBOL_NUMBER_PER_CHANNEL := MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
signal prev_sym: std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0) := (others => '0');
-- components instanciation and mapping
begin
-- presynthesis checks
......@@ -71,7 +75,7 @@ architecture structure of ccsds_tx_mapper is
CHKMAPPERP2 : if (CCSDS_TX_MAPPER_MODULATION_TYPE /= 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE /= 2) generate
process
begin
report "ERROR: UNKNOWN MODULATION TYPE - 1=nPSK / 2=BPSK" severity failure;
report "ERROR: UNKNOWN MODULATION TYPE - 1=QPSK/QAM / 2=BPSK" severity failure;
wait;
end process;
end generate CHKMAPPERP2;
......@@ -91,19 +95,40 @@ architecture structure of ccsds_tx_mapper is
if (rst_i = '1') then
sym_i_o <= (others => '0');
sym_q_o <= (others => '0');
prev_sym <= (others => '0');
symbol_counter <= MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
sym_val_o <= '0';
else
if (dat_val_i = '1') then
sym_val_o <= '1';
-- Differential coding
if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
-- BPSK
if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
prev_sym <= dat_i(symbol_counter-1 downto symbol_counter-1);
-- QPSK/QAM
else
prev_sym <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
end if;
-- BPSK mapping
if (CCSDS_TX_MAPPER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_MAPPER_MODULATION_TYPE = 2) then
sym_i_o(0) <= dat_i(symbol_counter-1);
sym_q_o(0) <= '0';
-- nPSK mapping
if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
sym_i_o(0 downto 0) <= dat_i(symbol_counter-1 downto symbol_counter-1) xor prev_sym;
else
sym_i_o(0) <= dat_i(symbol_counter-1);
end if;
-- QPSK/QAM mapping
else
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
if (CCSDS_TX_MAPPER_DIFFERENTIAL_CODER = true) then
--TODO HERE: GRAY MAPPING
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL) xor prev_sym;
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL) xor dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
else
sym_i_o <= dat_i(symbol_counter*CCSDS_TX_MAPPER_BITS_PER_SYMBOL*2-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
sym_q_o <= dat_i(symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto symbol_counter*2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL-2*CCSDS_TX_MAPPER_BITS_PER_SYMBOL);
end if;
end if;
if (symbol_counter = 1) then
symbol_counter <= MAPPER_SYMBOL_NUMBER_PER_CHANNEL;
......
......@@ -3,7 +3,7 @@
---- Design Name: ccsds_tx_physical_layer
---- Version: 1.0.0
---- Description:
---- TO BE DONE
---- CCSDS TX physical layer
-------------------------------
---- Author(s):
---- Guillaume REMBERT
......
......@@ -78,6 +78,8 @@ module orpsoc_top #(
`ifdef I2C0
inout i2c0_sda_io,
inout i2c0_scl_io,
output accelerometer_cs_o,
input accelerometer_irq_i,
`endif
`ifdef CCSDS_RXTX0
......@@ -238,25 +240,30 @@ wire or1k_rst;
assign or1k_rst = wb_rst | or1k_dbg_rst;
mor1kx #(
.FEATURE_DEBUGUNIT("ENABLED"),
// Base definition
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0("CAPPUCCINO"),
.OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
.OPTION_RESET_PC(32'hf0000000),
// Options activated
.FEATURE_CMOV("ENABLED"),
.FEATURE_INSTRUCTIONCACHE("ENABLED"),
.OPTION_ICACHE_BLOCK_WIDTH(5),
.OPTION_ICACHE_SET_WIDTH(8),
.OPTION_ICACHE_WAYS(2),
.OPTION_ICACHE_LIMIT_WIDTH(32),
.FEATURE_IMMU("ENABLED"),
.FEATURE_DATACACHE("ENABLED"),
.OPTION_DCACHE_BLOCK_WIDTH(5),
.OPTION_DCACHE_SET_WIDTH(8),
.OPTION_DCACHE_WAYS(2),
.OPTION_DCACHE_LIMIT_WIDTH(31),
.FEATURE_DEBUGUNIT("ENABLED"),
.FEATURE_DMMU("ENABLED"),
.OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0("CAPPUCCINO"),
.OPTION_RESET_PC(32'hf0000000)
.FEATURE_IMMU("ENABLED"),
.FEATURE_INSTRUCTIONCACHE("ENABLED"),
.OPTION_ICACHE_BLOCK_WIDTH(5),
.OPTION_ICACHE_SET_WIDTH(8),
.OPTION_ICACHE_WAYS(2),
.OPTION_ICACHE_LIMIT_WIDTH(32),
.FEATURE_FPU("NONE"),
.FEATURE_MAC("NONE"),
.FEATURE_MULTICORE("NONE")
) mor1kx0 (
.iwbm_adr_o(wb_m2s_or1k_i_adr),
.iwbm_stb_o(wb_m2s_or1k_i_stb),
......@@ -571,6 +578,9 @@ i2c0
);
// choose I2C operation mode
assign accelerometer_cs_o = 1;
assign wb_s2m_i2c0_err = 0;
assign wb_s2m_i2c0_rty = 0;
......@@ -741,10 +751,11 @@ assign or1k_irq[8] = 0;
assign or1k_irq[9] = 0;
`ifdef I2C0
assign or1k_irq[10] = i2c0_irq;
assign or1k_irq[11] = accelerometer_irq_i;
`else
assign or1k_irq[10] = 0;
assign or1k_irq[11] = 0;
`endif
assign or1k_irq[11] = 0;
assign or1k_irq[12] = 0;
assign or1k_irq[13] = 0;
assign or1k_irq[14] = 0;
......
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