Commit e8c1492a authored by Guillaume REMBERT's avatar Guillaume REMBERT

Framer optimization + manager serdes implementation

parent d0338ebd
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......@@ -4,6 +4,10 @@
---- Version: 1.0.0
---- Description:
---- FIFO circular buffer
---- Input: 1 clk / [STORE: dat_val_i <= '1' / dat_i <= "STOREDDATA" ] / [READ: nxt_i <= '1']
---- Timing requirements: 1 clock cycle
---- Output: [READ: dat_val_o <= "1" / dat_o <= "STOREDDATA"]
---- Ressources requirements: CCSDS_RXTX_BUFFER_DATA_BUS_SIZE*(CCSDS_RXTX_BUFFER_SIZE+1) + 2*|log(CCSDS_RXTX_BUFFER_SIZE-1)/log(2)| + 2 + 3 + CCSDS_RXTX_BUFFER_DATA_BUS_SIZE registers
-------------------------------
---- Author(s):
---- Guillaume REMBERT
......@@ -25,8 +29,8 @@ use ieee.std_logic_1164.all;
--=============================================================================
entity ccsds_rxtx_buffer is
generic(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer;
CCSDS_RXTX_BUFFER_SIZE : integer
constant CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer; -- in bits
constant CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
-- inputs
......@@ -106,7 +110,7 @@ architecture rtl of ccsds_rxtx_buffer is
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
buffer_data <= (others => (others => '0'));
-- buffer_data <= (others => (others => '0'));
buf_ful_o <= '0';
buffer_write_pos <= 0;
else
......
This diff is collapsed.
......@@ -3,8 +3,11 @@
---- Design Name: ccsds_rxtx_serdes
---- Version: 1.0.0
---- Description:
---- This is the data serialiser/deserialiser
---- requires CCSDS_RXTX_SERDES_DEPTH clk cycles to finish
---- Constant rate data serialiser/deserialiser
---- Input: 1 clk / [SER2PAR: dat_ser_val_i <= '1' / dat_ser_i <= 'NEXTSERIALDATA' ] / [PAR2SER: dat_par_val_i <= '1' / dat_par_i <= "PARALLELDATA"]
---- Timing requirements: SER2PAR: 1 clock cycle - PAR2SER: CCSDS_RXTX_SERDES_DEPTH clock cycles
---- Output: [SER2PAR: dat_par_val_o <= "1" / dat_par_o <= "PARALLELIZEDDATA"] / [PAR2SER: dat_ser_val_o <= "1" / dat_ser_o <= "SERIALIZEDDATA"]
---- Ressources requirements: CCSDS_RXTX_SERDES_DEPTH + 2*|log(CCSDS_RXTX_SERDES_DEPTH-1)/log(2)| + 2 registers
-------------------------------
---- Author(s):
---- Guillaume Rembert
......@@ -28,7 +31,7 @@ use work.ccsds_rxtx_parameters.all;
--=============================================================================
entity ccsds_rxtx_serdes is
generic (
CCSDS_RXTX_SERDES_DEPTH : integer
constant CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
-- inputs
......@@ -86,7 +89,7 @@ architecture rtl of ccsds_rxtx_serdes is
dat_ser_o <= '0';
wire_data_ser_valid <= '0';
parallel_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
serdes_memory := (others => '0');
-- serdes_memory := (others => '0');
else
if (dat_par_val_i = '1') and (parallel_data_pointer = CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
......
......@@ -220,7 +220,7 @@ begin
ccsds_rxtx_dyn_wb_state := 0;
-- reinitialize all outputs
wire_tx_ext <= CCSDS_RXTX_CST_TX_AUTO_EXTERNAL;
if (CCSDS_RXTX_CST_TX_AUTO_EXTERNAL = '0') then
if (CCSDS_RXTX_CST_TX_AUTO_EXTERNAL = '0') then
wire_tx_data_valid <= '0';
else
wire_tx_data_valid <= '1';
......
......@@ -26,10 +26,10 @@ use ieee.math_real.all;
--=============================================================================
entity ccsds_tx_datalink_layer is
generic (
CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer := 32; -- in bits
CCSDS_TX_DATALINK_DATA_LENGTH: integer := 24; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer := 32; -- in bits
constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 24; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
);
port(
-- inputs
......@@ -163,14 +163,4 @@ architecture structure of ccsds_tx_datalink_layer is
-- constant TX_DATALINK_CCSDS_ASM_SEQUENCE : std_logic_vector(31 downto 0) := "00011010110011111111110000011101"; -- TRAINING SEQUENCE (FOR SYNCHRONIZATION PURPOSES)
--=============================================================================
-- Begin of datalinkp
-- DESCRIPTION TBD
--=============================================================================
-- read:
-- write:
-- r/w:
DATALINKP : process (clk_i)
begin
end process;
end structure;
......@@ -32,8 +32,8 @@ use ieee.std_logic_1164.all;
--=============================================================================
entity ccsds_tx_footer is
generic(
CCSDS_TX_FOOTER_DATA_LENGTH: integer; -- in Bytes
CCSDS_TX_FOOTER_LENGTH: integer -- in Bytes
constant CCSDS_TX_FOOTER_DATA_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FOOTER_LENGTH: integer -- in Bytes
);
port(
-- inputs
......@@ -54,8 +54,8 @@ end ccsds_tx_footer;
architecture rtl of ccsds_tx_footer is
component ccsds_rxtx_crc is
generic(
CCSDS_RXTX_CRC_LENGTH: integer;
CCSDS_RXTX_CRC_DATA_LENGTH: integer
constant CCSDS_RXTX_CRC_LENGTH: integer;
constant CCSDS_RXTX_CRC_DATA_LENGTH: integer
);
port(
clk_i: in std_logic;
......
This diff is collapsed.
......@@ -3,7 +3,7 @@
---- Design Name: ccsds_tx_manager
---- Version: 1.0.0
---- Description:
---- TBD - in charge of clock enable/disable + input switch / ser to par conversion
---- In charge of clock forwarding to reduce power draw + select TX input data
-------------------------------
---- Author(s):
---- Guillaume REMBERT
......@@ -13,8 +13,8 @@
-------------------------------
---- Changes list:
---- 2016/10/16: initial release
---- 2016/10/31: add serdes sub-component
-------------------------------
--TODO: use dedicated serdes component
-- libraries used
library ieee;
......@@ -48,65 +48,77 @@ end ccsds_tx_manager;
-- architecture declaration / internal connections
--=============================================================================
architecture structure of ccsds_tx_manager is
component ccsds_rxtx_serdes is
generic (
constant CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
clk_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_i: in std_logic;
dat_ser_i: in std_logic;
dat_ser_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_o: out std_logic;
dat_ser_o: out std_logic;
dat_ser_val_o: out std_logic
);
end component;
-- interconnection signals
signal gated_clock: std_logic;
signal wire_serdes_dat_par_o: std_logic_vector(CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 downto 0);
signal wire_serdes_dat_par_val_o: std_logic;
signal wire_serdes_dat_ser_val_i: std_logic;
-- components instanciation and mapping
begin
-- components instanciation and mapping
serdes_001: ccsds_rxtx_serdes
generic map(
CCSDS_RXTX_SERDES_DEPTH => CCSDS_TX_MANAGER_DATA_BUS_SIZE
)
port map(
clk_i => gated_clock,
dat_par_i => (others => '0'),
dat_par_val_i => '0',
dat_ser_i => dat_ser_i,
dat_ser_val_i => wire_serdes_dat_ser_val_i,
rst_i => rst_i,
dat_par_o => wire_serdes_dat_par_o,
dat_par_val_o => wire_serdes_dat_par_val_o
);
ena_o <= ena_i;
clk_o <= clk_i and ena_i;
gated_clock <= clk_i and ena_i;
--=============================================================================
-- Begin of enablep
-- Enable/disable clk forwarding
--=============================================================================
-- read: ena_i
-- write: clk_o, enabled_o
-- r/w:
ENABLEP : process (ena_i, clk_i)
begin
if (ena_i = '1') then
clk_o <= clk_i;
ena_o <= '1';
else
clk_o <= '0';
ena_o <= '0';
end if;
end process;
--=============================================================================
-- Begin of serparp
-- Serial to parallel data if in_sel_i = 1 / first input bit as MSB
-- Begin of selectp
-- Input selection
--=============================================================================
-- read: clk_i, rst_i, ena_i, dat_val_i, in_sel_i
-- write: dat_o, dat_val_o
-- read: rst_i, ena_i, in_sel_i, dat_val_i
-- write: dat_o, dat_val_o, wire_serdes_dat_ser_val_i
-- r/w:
SERPARP : process (clk_i)
SELECTP : process (gated_clock)
-- variables instantiation
variable circular_pointer: integer range 0 to CCSDS_TX_MANAGER_DATA_BUS_SIZE-1 := CCSDS_TX_MANAGER_DATA_BUS_SIZE-1;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
if rising_edge(gated_clock) then
if (rst_i = '1') then
dat_o <= (others => '0');
dat_val_o <= '0';
wire_serdes_dat_ser_val_i <= '0';
else
if (ena_i = '1') then
if (dat_val_i = '1') then
if (in_sel_i = '1') then
dat_o(circular_pointer) <= dat_ser_i;
if (circular_pointer = 0) then
dat_val_o <= '1';
circular_pointer := CCSDS_TX_MANAGER_DATA_BUS_SIZE-1;
else
dat_val_o <= '0';
circular_pointer := circular_pointer - 1;
end if;
else
dat_val_o <= '1';
dat_o <= dat_par_i;
end if;
else
dat_val_o <= '0';
end if;
if (in_sel_i = '1') then
wire_serdes_dat_ser_val_i <= '1';
dat_o <= wire_serdes_dat_par_o;
dat_val_o <= wire_serdes_dat_par_val_o;
else
dat_val_o <= '0';
wire_serdes_dat_ser_val_i <= '0';
dat_val_o <= dat_val_i;
dat_o <= dat_par_i;
end if;
end if;
end if;
......
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