...
 
Commits (3)
......@@ -166,3 +166,10 @@ FIXME: TBD / variables / functions / comments / ...
-------------------------------
FIXME: TBD / HW and SW requirements, OS setup, build, install, test
-------------------------------
1. Development environment setup
1.1 Get sources
git clone https://sources.euryecetelecom.com/euryspace/euryspace.git
1.2 Install development tools
cd euryspace
bash euryspace -a install -e dev -o centos7 | bash euryspace -a install -e dev -o debian9
-------------------------------
......@@ -5,8 +5,7 @@
# Version: 1.0.0
# Description:
# EurySPACE management tool
# Validated on CentOS 7
# TODO: Ubuntu 16 LTS
# Validated on CentOS 7 and Debian 9
################################
# Author(s):
# Guillaume REMBERT
......@@ -14,9 +13,6 @@
# Licence:
# MIT
################################
# Changes list:
# 2017/09/04: initial release
################################
#Conf for sources / builds
#Install environment (dev / prod) + all / only sub-parts
......@@ -32,23 +28,27 @@ function show_help {
echo "ACTION: install"
echo "DESTINATION: destination folder (default: /home/euryspace)"
echo "ENVIRONMENT: dev|development, prod|production (default value)"
echo "OPERATING_SYSTEM: centos7 (default value), ubuntu16"
echo "OPERATING_SYSTEM: centos7 (default value), debian9"
echo "TARGET: all (default value), space|space_segment, ground|ground_segment, user|user_segment"
echo "USER: user used to start (default: astronaut)"
}
START_TIME=$(date +%s)
####################
# SCRIPT VARIABLES #
####################
#####################################
# SCRIPT VARIABLES + DEFAULT VALUES #
#####################################
EURYSPACE_PRODUCTION=true
EURYSPACE_OPERATING_SYSTEM="centos7"
EURYSPACE_USER="astronaut"
EURYSPACE_DESTINATION="/home/euryspace"
EURYSPACE_BUILD_PARALLELISM=2
#########################
# SCRIPT INITIALISATION #
#########################
#Check script is run as root
if [[ $EUID -ne 0 ]]; then
echo "This script must be run as root" 1>&2
......@@ -60,7 +60,7 @@ SCRIPT_PATH=$(dirname "$SCRIPT_COMMAND")
#Should not be changed except if you changed sw folder layout
SCRIPT_CONF_PATH=$SCRIPT_PATH/cfg/sw/euryspace.conf
#Get input parameters
while getopts :a:e:ht: ARGUMENT
while getopts :a:e:ho:t: ARGUMENT
do
case "${ARGUMENT}" in
a) SCRIPT_ACTION=${OPTARG}
......@@ -97,7 +97,7 @@ do
;;
o) EURYSPACE_OPERATING_SYSTEM=${OPTARG}
case "${EURYSPACE_OPERATING_SYSTEM}" in
ubuntu16|centos7)
debian9|centos7)
;;
*)
echo "Unmanaged operating system: ${EURYSPACE_OPERATING_SYSTEM}" 1>&2
......@@ -116,10 +116,18 @@ do
;;
esac
done
if [ $OPTIND -eq 1 ]; then
show_help
exit 1
fi
####################
# SCRIPT EXECUTION #
####################
case "${SCRIPT_ACTION}" in
install)
$SCRIPT_PATH/sw/src/tools/euryspace_install.sh ${EURYSPACE_OPERATING_SYSTEM} ${EURYSPACE_PRODUCTION} ${EURYSPACE_USER} ${EURYSPACE_DESTINATION}
$SCRIPT_PATH/sw/src/tools/euryspace_install.sh ${EURYSPACE_OPERATING_SYSTEM} ${EURYSPACE_PRODUCTION} ${EURYSPACE_USER} ${EURYSPACE_DESTINATION} ${EURYSPACE_BUILD_PARALLELISM}
;;
esac
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
-- libraries used
library ieee;
......
This diff is collapsed.
......@@ -15,10 +15,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
---- 2016/10/20: major corrections and optimizations
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
package ccsds_rxtx_constants is
constant RXTX_CST: integer := 1; -- DUMMY USELESS CONSTANT
......
......@@ -16,11 +16,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/10/18: initial release
---- 2016/10/25: external padding data mode
---- 2016/10/30: ressources usage optimization
-------------------------------
--TODO: Implement DIRECT computation?
--TODO: CRC LENGTH not being multiple of Byte
......
......@@ -11,12 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/12/28: initial release
---- 2016/10/20: added reverse_std_logic_vector function + rework sim_generate_random_std_logic_vector for > 32 bits vectors
---- 2016/11/17: added convert_boolean_to_std_logic function
---- 2017/01/15: added convert_std_logic_vector_array_to_std_logic_vector
-------------------------------
-- libraries used
library ieee;
......
......@@ -15,9 +15,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- Test ressources:
-- GNURADIO GLFSR block
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,10 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/20: rework / remove non-systems parameters / each component has his own parameters set at proper level
-------------------------------
-- libraries used
library ieee;
......
......@@ -15,10 +15,7 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/18: initial release
---- 2016/10/27: review + add ser2par
-------------------------------
--TODO: change data pointer use to shift register and counter
-- libraries used
library ieee;
......
......@@ -15,9 +15,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- Filter impulse response - SRRC(t):
-- t = 0 => SRRC(0) = (1-B + 4*B/PI)
-- t = +/-Ts/(4*B) => SRRC(+/-Ts/(4*B)) = (B/racine(2) * (1+2/PI) * sin(PI/(4*B)) + (1-2/PI) * cos(PI/(4*B)))
......
......@@ -15,10 +15,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/26: initial release - only basic RX-TX capabilities through direct R/W on WB Bus / no dynamic configuration capabilities
---- 2016/10/18: major rework / implementation of new architecture
-------------------------------
-- TODO: additionnal modulations: ASK, FSK, GMSK, OFDM, CDMA
-- TODO: dynamic modulation and coding
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2017/01/15: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,10 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/19: rework
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
......@@ -25,6 +22,7 @@ use ieee.std_logic_1164.all;
entity ccsds_tx_coder is
generic(
constant CCSDS_TX_CODER_ASM_LENGTH: integer; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_CODER_CONVOLUTIONNAL_RATE_OUTPUT: integer; -- in bits
constant CCSDS_TX_CODER_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword (should be equal to bits per symbol of lower link)
constant CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean -- Enable differential coder
......@@ -36,7 +34,7 @@ entity ccsds_tx_coder is
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector((CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8)*CCSDS_TX_CODER_CONVOLUTIONNAL_RATE_OUTPUT-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_coder;
......@@ -45,6 +43,21 @@ end ccsds_tx_coder;
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_coder is
component ccsds_tx_coder_convolutional is
generic(
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE: integer;
CCSDS_TX_CODER_CONV_RATE_OUTPUT: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE*CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_coder_differential is
generic(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
......@@ -94,6 +107,7 @@ architecture structure of ccsds_tx_coder is
signal wire_randomizer_dat_val_o: std_logic;
signal wire_synchronizer_dat_o: std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
signal wire_synchronizer_dat_val_o: std_logic;
--HERE CONV
-- components instanciation and mapping
begin
tx_coder_randomizer_0: ccsds_tx_randomizer
......@@ -119,8 +133,22 @@ architecture structure of ccsds_tx_coder is
rst_i => rst_i,
dat_val_i => wire_randomizer_dat_val_o,
dat_i => wire_randomizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
dat_val_o => wire_synchronizer_dat_val_o,
dat_o => wire_synchronizer_dat_o
);
tx_coder_convolutionnal_0: ccsds_tx_coder_convolutional
generic map(
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8,
CCSDS_TX_CODER_CONV_RATE_OUTPUT => CCSDS_TX_CODER_CONVOLUTIONNAL_RATE_OUTPUT
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_i => wire_synchronizer_dat_o,
dat_val_i => wire_synchronizer_dat_val_o,
-- bus_o => ,
dat_o => dat_o,
dat_val_o => dat_val_o
);
end generate NODIFFCODERGENP;
DIFFCODERGENP: if (CCSDS_TX_CODER_DIFFERENTIAL_ENABLED = true) generate
......@@ -147,8 +175,22 @@ architecture structure of ccsds_tx_coder is
rst_i => rst_i,
dat_val_i => wire_synchronizer_dat_val_o,
dat_i => wire_synchronizer_dat_o,
dat_val_o => dat_val_o,
dat_o => dat_o
dat_val_o => wire_coder_diff_dat_val_o,
dat_o => wire_coder_diff_dat_o
);
tx_coder_convolutionnal_0: ccsds_tx_coder_convolutional
generic map(
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE => CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8,
CCSDS_TX_CODER_CONV_RATE_OUTPUT => CCSDS_TX_CODER_CONVOLUTIONNAL_RATE_OUTPUT
)
port map(
clk_i => clk_i,
rst_i => rst_i,
dat_i => wire_coder_diff_dat_o,
dat_val_i => wire_coder_diff_dat_val_o,
-- bus_o => ,
dat_o => dat_o,
dat_val_o => dat_val_o
);
end generate DIFFCODERGENP;
-- presynthesis checks
......
......@@ -9,9 +9,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2017/01/15: initial release
-------------------------------
-- TODO: puncturation + input rate /= 1
-- libraries used
......
......@@ -9,9 +9,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,10 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
---- 2016/10/21: rework based on TX final architecture
-------------------------------
-- libraries used
library ieee;
......@@ -26,6 +22,7 @@ use ieee.std_logic_1164.all;
entity ccsds_tx_datalink_layer is
generic (
constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
constant CCSDS_TX_DATALINK_CODER_CONVOLUTIONNAL_RATE_OUTPUT: integer := 2; -- Convolutional coder output rate per input bit (bits)
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
......@@ -74,7 +71,8 @@ architecture structure of ccsds_tx_datalink_layer is
generic(
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
CCSDS_TX_CODER_DATA_BUS_SIZE: integer;
CCSDS_TX_CODER_CONVOLUTIONNAL_RATE_OUTPUT: integer;
CCSDS_TX_CODER_ASM_LENGTH: integer
);
port(
......@@ -82,14 +80,19 @@ architecture structure of ccsds_tx_datalink_layer is
dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector((CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8)*CCSDS_TX_DATALINK_CODER_CONVOLUTIONNAL_RATE_OUTPUT-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8;
constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8*CCSDS_TX_DATALINK_CODER_CONVOLUTIONNAL_RATE_OUTPUT;
constant FRAME_OUTPUT_WORDS: integer := FRAME_OUTPUT_SIZE/CCSDS_TX_DATALINK_DATA_BUS_SIZE;
constant TRIGGER_COUNTER_CLOCK_DURATION: integer := 8;
-- internal registers
signal current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-1 downto 0) := (others => '0');
signal new_frame: std_logic := '0';
-- interconnection signals
signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
......@@ -120,6 +123,7 @@ architecture structure of ccsds_tx_datalink_layer is
tx_datalink_coder_0: ccsds_tx_coder
generic map(
CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
CCSDS_TX_CODER_CONVOLUTIONNAL_RATE_OUTPUT => CCSDS_TX_DATALINK_CODER_CONVOLUTIONNAL_RATE_OUTPUT,
CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
......@@ -134,37 +138,49 @@ architecture structure of ccsds_tx_datalink_layer is
);
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of bitsoutputp
-- Generate valid bits output word by word on coder data_valid signal
-- Begin of bitsvalidp
-- Catch and signal to bitsoutputp valid bits to be outputed
--=============================================================================
-- read: rst_i, wire_coder_data_valid
-- write: dat_val_o
-- read: rst_i, wire_coder_data, wire_coder_data_valid
-- write: current_frame, new_frame
-- r/w:
BITSVALIDP: process (clk_dat_i)
variable trigger_counter_clock_cycles: integer range 0 to TRIGGER_COUNTER_CLOCK_DURATION := 0;
begin
-- on each clock rising edge
if rising_edge(clk_dat_i) then
-- reset signal received
if (rst_i = '1') then
dat_val_o <= '0';
new_frame <= '0';
trigger_counter_clock_cycles := 0;
else
if (wire_coder_data_valid = '1') then
dat_val_o <= '1';
current_frame <= wire_coder_data;
new_frame <= '1';
trigger_counter_clock_cycles := 0;
else
if (trigger_counter_clock_cycles = TRIGGER_COUNTER_CLOCK_DURATION) then
new_frame <= '0';
else
trigger_counter_clock_cycles := trigger_counter_clock_cycles + 1;
end if;
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of bitsoutputp
-- Generate bits output word by word based on coder output
--=============================================================================
-- read: rst_i, wire_coder_data
-- write: dat_o
-- read: rst_i, current_frame, new_frame
-- write: dat_o, dat_val_o
-- r/w:
BITSOUTPUTP: process (clk_bit_i)
variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
variable current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_bit_i) then
......@@ -172,12 +188,19 @@ architecture structure of ccsds_tx_datalink_layer is
if (rst_i = '1') then
next_word_pointer := FRAME_OUTPUT_WORDS - 1;
dat_o <= (others => '0');
dat_val_o <= '0';
else
-- generating valid bits output words
if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
next_word_pointer := FRAME_OUTPUT_WORDS - 2;
if (new_frame = '1') then
-- current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
-- dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
dat_o <= current_frame(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
next_word_pointer := FRAME_OUTPUT_WORDS - 2;
dat_val_o <= '1';
else
dat_val_o <= '0';
end if;
else
dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
if (next_word_pointer = 0) then
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/06: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,10 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/28: initial release
---- 2016/10/21: rework
-------------------------------
--TODO: operationnal control field
--TODO: security trailer
--[OPT] SECURITY TRAILER
......
......@@ -11,13 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
---- 2016/10/20: rework
---- 2016/10/24: multiple footers generation to ensure higher speed than input max data rate (CCSDS_TX_FRAMER_DATA_BUS_SIZE*CLK_FREQ bits/sec)
---- 2016/10/31: ressources optimization
---- 2016/11/03: add only idle data insertion
-------------------------------
--TODO: trailer as option
--HEADER (6 up to 70 bytes) / before data / f(idle)
--TRANSFER FRAME DATA FIELD => Variable
......
......@@ -11,11 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/28: initial release
---- 2016/10/21: rework
---- 2016/11/03: add idle data flag
-------------------------------
--TODO: static fixed virtual channel now - implement virtual channel service
--TODO: secondary header
--TODO: security header
......
......@@ -11,11 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/10/16: initial release
---- 2016/10/31: add serdes sub-component
---- 2016/11/05: add clock generator sub-component
-------------------------------
-- libraries used
library ieee;
......@@ -28,7 +23,7 @@ entity ccsds_tx_manager is
generic(
constant CCSDS_TX_MANAGER_BITS_PER_SYMBOL: integer;
constant CCSDS_TX_MANAGER_MODULATION_TYPE: integer;
constant CCSDS_TX_MANAGER_DATALINK_OVERHEAD_RATIO: integer := 2;
constant CCSDS_TX_MANAGER_DATALINK_OVERHEAD_RATIO: integer := 4;
constant CCSDS_TX_MANAGER_PARALLELISM_MAX_RATIO: integer := 16;
constant CCSDS_TX_MANAGER_OVERSAMPLING_RATIO: integer;
constant CCSDS_TX_MANAGER_DATA_BUS_SIZE : integer
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/18: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/17: initial release
-------------------------------
--TODO: Gray coder
-- libraries used
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
......
......@@ -11,9 +11,6 @@
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/11/05: initial release
-------------------------------
-- libraries used
library ieee;
......
#!/bin/bash
cd ./build/euryspace_0/src/ccsds_rxtx_0
HDLFILES="ccsds_rxtx_types.vhd ccsds_rxtx_functions.vhd ccsds_tx_coder_convolutional.vhd ccsds_rxtx_parameters.vhd ccsds_tx_coder_differential.vhd ccsds_rxtx_srrc.vhd ccsds_rxtx_oversampler.vhd ccsds_tx_filter.vhd ccsds_rxtx_clock_divider.vhd ccsds_tx_mapper_bits_symbols.vhd ccsds_tx_mapper_symbols_samples.vhd ccsds_tx_randomizer.vhd ccsds_rxtx_lfsr.vhd ccsds_tx_synchronizer.vhd ccsds_rxtx_constants.vhd ccsds_rxtx_serdes.vhd ccsds_rxtx_crc.vhd ccsds_tx_coder.vhd ccsds_tx_framer.vhd ccsds_tx_header.vhd ccsds_tx_footer.vhd ccsds_rxtx_buffer.vhd ccsds_rx_datalink_layer.vhd ccsds_rx_physical_layer.vhd ccsds_rx.vhd ccsds_tx_datalink_layer.vhd ccsds_tx_physical_layer.vhd ccsds_tx_manager.vhd ccsds_tx.vhd ccsds_rxtx_top.vhd ccsds_rxtx_bench.vhd"
echo "START: Importing HDL files"
ghdl -i -v $HDLFILES
echo "START: Analyzing HDL files"
ghdl -a -v $HDLFILES
echo "START: Elaborating testbench entity"
ghdl -e -v ccsds_rxtx_bench
echo "START: Running simulation with testbench entity"
ghdl -r -v ccsds_rxtx_bench --vcd=ccsds_rxtx_sim_results.vcd --stop-time=1000000ns --unbuffered
#echo "START: Opening simulation results window"
#gtkwave /home/grembert/or1k/build_socs/build/euryspace/src/ccsds_rxtx/ccsds_rxtx_sim_results.vcd &
......@@ -10,8 +10,8 @@ slaves =
sdram_dbus
uart0
gpio0
spi0
i2c0
spi0
ccsds_rxtx0
; debug master
......@@ -22,8 +22,8 @@ slaves =
rom0
uart0
gpio0
spi0
i2c0
spi0
ccsds_rxtx0
; SDRAM
......
BLOCK START ADDRESS END ADDRESS
Page_0 0x00000000 0x0004B1ED
sw.hex 0x00080000 0x000A9ED0
Page_0 0x00000000 0x00059DFC
sw.hex 0x00080000 0x000DBDED
Configuration device: EP4CE22
......@@ -11,6 +11,6 @@ Quad-Serial configuration device dummy clock cycle: 8
Notes:
- Data checksum for this conversion is 0x7A014E25
- Data checksum for this conversion is 0x775F8FEF
- All the addresses in this file are byte addresses
\ No newline at end of file
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//Checks/example of LED on/off + various TX/RX basic configuration and transmission tests
#include <stdio.h>
#include <or1k-support.h>
......@@ -10,19 +12,17 @@ const unsigned int tx_rand_seed = 0;
char* leds_gpio0_addr = (char*) 0x91000000;
int* ccsds_rxtx0_rxtx_addr = (int*) 0xc0000000;
// char* ccsds_rxtx0_rxtx_addr = (char*) 0xc0000000;
//char* ccsds_rxtx0_rxtx_addr = (char*) 0xc0000000;
//int* ccsds_rxtx0_rx_conf_addr = (int*) 0xc0000001;
//int* ccsds_rxtx0_tx_conf_addr = (int*) 0xc0000002;
int init_random(unsigned int seed)
{
int init_random(unsigned int seed){
srand (seed);
return 0;
}
int sleep(int cycle_num)
{
int sleep(int cycle_num){
int count = 0;
while (count < cycle_num)
{
......@@ -31,12 +31,10 @@ int sleep(int cycle_num)
return 0;
}
int visual_control_seq(int type)
{
int visual_control_seq(int type){
//set to write IO
*(leds_gpio0_addr+1) = 0xff;
switch (type)
{
switch (type){
//init sequence
case 0:
//ON
......@@ -79,12 +77,10 @@ int visual_control_seq(int type)
return 0;
}
int receive_data(int type)
{
int receive_data(int type){
int rx_data;
rx_data = *(ccsds_rxtx0_rxtx_addr);
switch (type)
{
switch (type){
//default value
case 0:
if (rx_data == default_rx_value)
......@@ -105,11 +101,9 @@ int receive_data(int type)
}
int send_data(int type)
{
int send_data(int type){
int tx_data;
switch (type)
{
switch (type){
//all 0 datagram
case 0:
tx_data = 0x00000000;
......@@ -129,8 +123,7 @@ int send_data(int type)
return 0;
}
int main(void)
{
int main(void){
unsigned int loop_counter = 0;
printf("_______________________________________\n\n");
......@@ -138,67 +131,51 @@ int main(void)
printf("_______________________________________\n\n");
printf("START: visual control sequence - init sequence\n");
if (visual_control_seq(0) == 0)
{
if (visual_control_seq(0) == 0){
printf("OK: visual control sequence - init sequence\n");
}
else
{
} else {
printf("KO: visual control sequence - error - init sequence\n");
}
printf("DONE: visual control sequence - init sequence\n");
printf("START: RX/TX control sequence - default init parameters\n");
if (receive_data(0) == 0)
{
if (receive_data(0) == 0){
printf("OK: RX/TX control sequence - default init parameters\n");
}
else
{
} else {
printf("KO: RX/TX control sequence - error - default init parameters\n");
}
printf("DONE: RX/TX control sequence - default init parameters\n");
printf("START: RX/TX control sequence - tx data transmission\n");
if (send_data(0) == 0)
{
if (send_data(0) == 0){
printf("OK: RX/TX control sequence - time domain analysis - tx data changed to all 0\n");
printf("CHECK: RX/TX control sequence - time domain analysis - TX data are all 0 - inspect signal level\n");
sleep(sleep_count);
}
else
{
} else {
printf("KO: RX/TX control sequence - time domain analysis - error - tx data not changed to all 0\n");
}
if (send_data(1) == 0)
{
if (send_data(1) == 0){
printf("OK: RX/TX control sequence - time domain analysis - tx data changed to all 1\n");
printf("CHECK: RX/TX control sequence - time domain analysis - TX data are all 1 - inspect signal level\n");
sleep(sleep_count);
}
else
{
} else {
printf("KO: RX/TX control sequence - time domain analysis - error - tx data not changed to all 1\n");
}
printf("CHECK: RX/TX control sequence - frequency domain analysis - changing TX data alternation - inspect signal spectrum\n");
loop_counter = 0;
while (send_data(0) == 0 && send_data(1) == 0 && loop_counter < 10000000)
{
while (send_data(0) == 0 && send_data(1) == 0 && loop_counter < 10000000){
loop_counter++;
// sleep(1);
}
printf("CHECK: RX/TX control sequence - frequency domain analysis - changing TX data randomly - inspect signal spectrum\n");
init_random(tx_rand_seed);
while (send_data(2) == 0)
{
while (send_data(2) == 0){
// sleep(1);
}
// sleep(sleep_count);
// printf("Bad RX read: %h\n", *(ccsds_rxtx0_rxtx_addr+1));
......@@ -255,7 +232,6 @@ int main(void)
// wait some time
*/
printf("START: visual control sequence - stop sequence\n");
visual_control_seq(1);
printf("END: visual control sequence - stop sequence\n");
......
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