Programming languages used in this repository

  •   VHDL
    64.29 %
  •   Verilog
    24.32 %
  •   Shell
    3.71 %
  •   SystemVerilog
    2.29 %
  •   Tcl
    2.05 %
  •   C
    1.28 %
  •   Assembly
    1.27 %
  •   Coq
    0.52 %
  •   Makefile
    0.17 %
  •   Python
    0.09 %

Commit statistics for master Mar 13 - Dec 07

  • Total: 29 commits
  • Average per day: 0 commits
  • Authors: 3

Commits per day of month

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